Altera Video and Image Processing Suite - Manual (Page 206)

Parameter Value Description
Run-time reader
control
On or Off Run-time control for the read interface.
Avalon-MM master
local ports width
16–256,
Default = 256
Specify the width of the Avalon-MM ports used to access
external memory.
Frame Buffer Signals
Table 14-4: Common Signals for Frame Buffer IP Core
The table lists the input and output signals for the Frame Buffer IP core.
Note: The additional clock and reset signals are available when you turn on Use separate clocks for the Avalon-
MM master interfaces.
Signal Direction Description
clock
Input The main system clock. The IP core operates on the rising
edge of this signal.
reset
Input The IP core asynchronously resets when this signal is high.
You must deassert this signal synchronously to the rising
edge of the clock signal.
din_data
Input
din
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data into the IP core.
din_endofpacket
Input
din
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
din_ready
Output
din
port Avalon-ST
ready
signal. This signal indicates
when the IP core is ready to receive data.
din_startofpacket
Input
din
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
din_valid
Input
din
port Avalon-ST
valid
signal. This signal identifies the
cycles when the port must enter data.
dout_data
Output
dout
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
dout_endofpacket
Output
dout
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dout_valid
Output
dout
port Avalon-ST
valid
signal. The IP core asserts this
signal when it produces data.
UG-VIPSUITE
2015.05.04
Frame Buffer Signals 14-9
Frame Buffer IP Cores Altera Corporation
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