Altera Video and Image Processing Suite - Manual (Page 71)

Note: For Clocked Video Output IP core, you can also read the current level of the FIFO from the
Used
Words
register. This register is not available for Clocked Video Output II IP core.
Overflow
The FIFO can accommodate any bursts as long as the input rate of the upstream Avalon-ST Video
components is equal to or higher than that of the incoming clocked video. If this is not the case, the FIFO
overflows. If overflow occurs, the CVI IP cores produce an early
endofpacket
signal to complete the
current frame. It then waits for the next start of frame (or field) before resynchronizing to the incoming
clocked video and beginning to produce data again. The overflow is recorded in bit [9] of the
Status
register. This bit is sticky, and if an overflow occurs, it stays at 1 until the bit is cleared by writing a 0 to it.
In addition to the overflow bit, you can read the current level of the FIFO from the
Used Words
register.
The height and width parameters at the point the frame was completed early will be used in the control
packet of the subsequent frame. If you are reading back the detected resolution, then these unusual
resolution values can make the CVI IP cores seem to be operating incorrectly where in fact, the
downstream system is failing to service the CVI IP cores at the necessary rate.
Timing Constraints
You need to constrain the Clocked Video Interface IP cores.
Clocked Video Input and Clocked Video Output IP Cores
To constrain these IP cores correctly, add the following files to your Quartus II project:
•
<install_dir>\ip\altera\clocked_video_input\ alt_vip_cvi.sdc
•
<install_dir>\ip\altera\clocked_video_output\alt_vip_cvo.sdc
When you apply the .sdc file, you may see some warning messages similar to the format below:
• Warning: At least one of the filters had some problems and could not be matched.
• Warning: * could not be matched with a keeper.
These warnings are expected, because in certain configurations the Quartus II software optimizes unused
registers and they no longer remain in your design.
Clocked Video Input II and Clocked Video Output II IP Cores
For these IP cores, the .sdc files are automatically included by their respective .qip files. After adding the
Qsys system to your design in Quartus, verify that the alt_vip_cvi_core.sdc or alt_vip_cvo_core.sdc has been
included.
Altera recommends that you place a frame buffer in any CVI to CVO system. Because the CVO II IP core
generates sync signals for a complete frame, even when video frames end early, it is possible for the CVO
II IP core to continually generate backpressure to the CVI II IP core so that it keeps ending packets early.
Handling Ancillary Packets
The Clocked Video Interface IP cores use Active Format Description (AFD) Extractor and Inserter
examples to handle ancillary packets.
4-12 Timing Constraints
UG-VIPSUITE
2015.05.04
Altera Corporation Clocked Video Interface IP Cores
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