Control synchronizer ip core, Control synchronizer ip core -1 – Altera Video and Image Processing Suite User Manual
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Control Synchronizer IP Core
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2015.05.04
UG-VIPSUITE
The Control Synchronizer IP core synchronizes the configuration change of IP cores with an event in a
video stream. For example, the IP core can synchronize the changing of a position of a video layer with
the changing of the size of the layer.
The Control Synchronizer IP core has the following ports:
• Avalon Video Streaming Input and Output port—passes through Avalon-ST Video data, and monitors
the data for trigger events.
• Avalon Master port—writes data to the Avalon Slave control ports of other IP cores when the Control
Synchronizer IP core detects a trigger event.
• Avalon Slave port—sets the data to be written and the addresses that the data must be written to when
the IP core detects a trigger event.
• Avalon Slave Control port—disables or enables the trigger condition. You can configure the IP core
before compilation to disable this port after every trigger event; disabling this port is useful if you want
the IP core to trigger only on a single event.
The following events trigger the Control Synchronizer IP core:
• the start of a video data packet.
• a change in the width or height field of a control data packet that describes the next video data packet.
When the Control Synchronizer IP core detects a trigger event, the following sequence of events take
place:
1. The IP core immediately stalls the Avalon-ST video data flowing through the IP core.
2. The stall freezes the state of other IP cores on the same video processing data path that do not have
buffering in between.
3. The IP core then writes the data stored in its Avalon Slave register map to the addresses that are also
specified in the register map.
4. After writing is complete, the IP core resumes the Avalon-ST video data flowing through it. This
ensures that any cores after the Control Synchronizer IP core have their control data updated before
the start of the video data packet to which the control data applies.
5. When all the writes from a Control Synchronizer IP core trigger are complete, an interrupt is triggered
or is initiated, which is the “completion of writes” interrupt.
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