Altera Video and Image Processing Suite - Manual (Page 220)

Signal Direction Description
reset
Input The IP core asynchronously resets when this signal is high.
You must deassert this signal synchronously to the rising
edge of the clock signal.
din_data
Input
din
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data into the IP core.
din_endofpacket
Input
din
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
din_ready
Output
din
port Avalon-ST
ready
signal. This signal indicates
when the IP core is ready to receive data.
din_startofpacket
Input
din
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
din_valid
Input
din
port Avalon-ST
valid
signal. This signal identifies the
cycles when the port must enter data.
dout_data
Output
dout
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
dout_endofpacket
Output
dout
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dout_valid
Output
dout
port Avalon-ST
valid
signal. The IP core asserts this
signal when it produces data.
Table 16-3: Interlacer Control Interface Signals
These signals are present only if you turn on Pass-through mode.
Signal Direction Description
control_av_address
Input
control
slave port Avalon-MM
address
bus. This bus
specifies a word offset into the slave address space.
control_av_chipselect
Input
control
slave port Avalon-MM
chipselect
signal. The
control
port ignores all other signals unless you assert
this signal.
control_av_readdata
Output
control
slave port Avalon-MM
readdata
bus. The IP
core uses these output lines for read transfers.
control_av_waitrequest
Output
control
slave port Avalon-MM
waitrequest
signal.
control_av_write
Input
control
slave port Avalon-MM
write
signal. When you
assert this signal, the
control
port accepts new data from
the
writedata
bus.
UG-VIPSUITE
2015.05.04
Interlacer Signals 16-3
Interlacer IP Core Altera Corporation
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