Altera Video and Image Processing Suite - Manual (Page 213)

Address Register Description
2
Interrupt
Bits 2 and 1 are the interrupt status bits:
• When bit 1 is asserted, the status update interrupt has
triggered.
• When bit 2 is asserted, the stable video interrupt has
triggered.
• The interrupts stay asserted until a 1 is written to these
bits.
3
Frame Counter
Read-only register updated at the end of each frame processed
by the reader. The counter is incremented if the frame is not
repeated.
4
Repeat Counter
Read-only register updated at the end of each frame processed
by the reader. The counter is incremented if the frame is
about to be repeated.
14-16 Frame Buffer Control Registers
UG-VIPSUITE
2015.05.04
Altera Corporation Frame Buffer IP Cores
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