Altera Video and Image Processing Suite - Manual (Page 91)

Signal Direction Description
is_eop
Input
dout
port Avalon-ST
endofpacket
signal. This signal is
asserted when the downstream device is ending a frame.
is_ready
Output
dout
port Avalon-ST
ready
signal. This signal is asserted
when the IP core function is able to receive data.
is_sop
Input
dout
port Avalon-ST
startofpacket
signal. Assert this
signal when the downstream device is starting a new
frame.
is_valid
Input
dout
port Avalon-ST
valid
signal. Assert this signal when
the downstream device produces data.
underflow
Output Clocked video underflow signal. A signal corresponding to
the underflow sticky bit of the
Status
register synchron‐
ized to
vid_clk
. This signal is for information only and
no action is required if it is asserted.
Note: Present only if you turn on Use control port.
vcoclk_div
Output A divided down version of
vid_clk
(
vcoclk
). Setting the
Vcoclk Divider
register to be the number of samples in a
line produces a horizontal reference on this signal. A PLL
uses this horizontal reference to synchronize its output
clock.
sof
Input Start of frame signal. A rising edge (0 to 1) indicates the
start of the video frame as configured by the SOF registers.
Connecting this signal to a CVI IP core allows the output
video to be synchronized to this signal.
sof_locked
Output Start of frame locked signal. When asserted, the
sof
signal
is valid and can be used.
status_update_int
Output
control
slave port Avalon-MM interrupt signal. When
asserted, the status registers of the IP core have been
updated and the master must read them to determine
what has occurred.
Note: Present only if you turn on Use control port.
vid_clk
Input Clocked video clock. All the video output signals are
synchronous to this clock.
vid_data
Output Clocked video data bus. This bus transfers video data into
the IP core.
vid_datavalid
Output Clocked video data valid signal. Assert this signal when a
valid sample of video data is present on
vid_data
.
4-32 Clocked Video Interface Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Clocked Video Interface IP Cores
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