Altera Video and Image Processing Suite - Manual (Page 65)

The CVO IP cores can be configured to support between 1 to 14 different modes and each mode has a
bank of registers that describe the output frame.
• Clocked Video Output IP Core
• When the IP core receives a new control packet on the Avalon-ST Video input, it searches the
mode registers for a mode that is valid. The valid mode must have a field width and height that
matches the width and height in the control packet.
• The
Video Mode Match
register shows the selected mode.
• If a matching mode is found, it restarts the video output with those format settings.
• If a matching mode is not found, the video output format is unchanged and a restart does not
occur.
• Clocked Video Output II IP Core
• When the IP core receives a new control packet on the Avalon-ST Video input, it searches the
mode registers for a mode that is valid. The valid mode must have a field width and height that
matches the width and height in the control packet.
• The
Video Mode Match
register shows the selected mode.
• If a matching mode is found, it completes the current frame; duplicating data if needed before
commencing output with the new settings at the beginning of the next frame.
• If a matching mode is not found, the video output format is unchanged.
4-6 Clocked Video Output Video Modes
UG-VIPSUITE
2015.05.04
Altera Corporation Clocked Video Interface IP Cores
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