Altera Video and Image Processing Suite - Manual (Page 211)

Address Register Description
2
Frame Counter
Read-only register updated at the end of each frame processed
by the writer. The counter is incremented if the frame is not
dropped and passed to the reader.
3
Drop Counter
Read-only register updated at the end of each frame processed
by the writer. The counter is incremented if the frame is
dropped.
4
Controlled Rate
Conversion
Bit 0 of this register determines whether dropping and
repeating of frames or fields is tightly controlled by the
specified input and output frame rates. Setting this bit to 0
switches off the controlled rate conversion, and returns the
triple-buffering algorithm to a free regime where dropping
and repeating is only determined by the status of the spare
buffer.
5
Input Frame Rate
Write-only register. A 16-bit integer value for the input frame
rate. This register cannot be read.
6
Output Frame Rate
Write-only register. A 16-bit integer value for the output
frame rate. This register cannot be read.
Table 14-9: Frame Buffer Control Register Map for the Reader
The table below describes the control register map for the reader component.
Address Register Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused.
Setting this bit to 0 causes the IP core to stop the next time
control information is updated. While stopped, the IP core
may continue to receive and drop frame at its input if you
enable frame dropping.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused.
2
Frame Counter
Read-only register updated at the end of each frame processed
by the reader. The counter is incremented if the frame is not
repeated.
3
Repeat Counter
Read-only register updated at the end of each frame processed
by the reader. The counter is incremented if the frame is
about to be repeated.
14-14 Frame Buffer Control Registers
UG-VIPSUITE
2015.05.04
Altera Corporation Frame Buffer IP Cores
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