Altera Video and Image Processing Suite - Manual (Page 177)

Signal Direction Description
din_valid
Input
din
port Avalon-ST
valid
signal. This signal identifies the
cycles when the port must enter data.
dout_data
Output
dout
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
dout_endofpacket
Output
dout
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dout_valid
Output
dout
port Avalon-ST
valid
signal. The IP core asserts this
signal when it produces data.
Table 12-6: Signals for Deinterlacer IP Core
Signal Direction Description
ker_writer_control_av_
address
Input
ker_writer_control
slave port Avalon-MM
address
bus. This bus specifies a word offset into the slave address
space.
ker_writer_control_av_
chipselect
Input
ker_writer_control
slave port Avalon-MM
chipselect
signal. The
ker_writer_control
port ignores all other
signals unless you assert this signal.
ker_writer_control_av_
readdata
Output
ker_writer_control
slave port Avalon-MM
readdata
bus. The IP core uses these output lines for read transfers.
ker_writer_control_av_
waitrequest
Output
ker_writer_control
slave port Avalon-MM
waitrequest
signal.
ker_writer_control_av_write
Input
ker_writer_control
slave port Avalon-MM
write
signal. When you assert this signal, the
ker_writer_
control
port accepts new data from the
writedata
bus.
ker_writer_control_av_
writedata
Input
ker_writer_control
slave port Avalon-MM
writedata
bus. The IP core uses these input lines for write transfers.
ma_control_av_address
Input
ma_control
slave port Avalon-MM
address
bus. This
bus specifies a word offset into the slave address space.
ma_control_av_chipselect
Input control slave port Avalon-MM
chipselect
signal. The
ma_control
port ignores all other signals unless you assert
this signal.
ma_control_av_readdata
Output
ma_control
slave port Avalon-MM
readdata
bus. The IP
core uses these output lines for read transfers.
ma_control_av_waitrequest
Output
ma_control
slave port Avalon-MM
waitrequest
signal.
12-18 Deinterlacing Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Deinterlacing IP Cores
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