Register 24 : limit values (read/write), Register 30, 31: fixed values (read/write), Register 80 : state-controlled action bits (write) – Rice Lake PR5230 Fieldbus Transmitter User Manual

Page 199: Pr 5230 instrument manual fieldbus interface

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PR 5230 Instrument Manual

Fieldbus Interface

Sartorius

EN-199

Register 24 ... 29: Limit Values (Read/Write)

Register 24

Limit 1 on

Register 25

Limit 1 off

Register 26

Limit 2 on

Register 27

Limit 2 off

Register 28

Limit 3 on

Register 29

Limit 3 off

Register 30, 31: Fixed Values (Read/Write)

Register 30

Fixed value for analog output; value (num) 0... 20000 corresponds to 20 mA

Register 31

Fixed value for fixtare; see also SetFixTare, GetFixTare (see page 197

)

Register 80 ... 89: State-Controlled Action Bits (Write)
For setting bits, see page 193.
Only setting and resetting of single bits is possible.
When changing a bit from 0 to 1, the corresponding action starts. After handling the command, the bit must
be reset. Application: the master writes cyclically.
The bit is set as

Write_Value_Select

with the specified number (see page 193), the bit is reset at the specified

number +128.

Register 80 SetZero

Set the gross weight to zero

Register 81 SetTare

Execute taring

Register 82 ResetTare

Reset tare

Register 83 SetTest

Start the ADC test

Register 84 ResetTest

Finish the ADC test

Register 85 ResetPwf

Reset the

PowerFail

bit (Register 1; the bit was set after power on)

Register 86 SetFixTare

Taring with weight in numerical address D31 'Fixtare'

Register 87 GetFixTare

The current gross weight is copied into numerical address D31.

Register 89 ResetError

The

CmdError

error bit is reset


Register 112 ... 121: Transition-Controlled Action Bits (Write)
For setting bits, see page 193.
As soon as the bit was set, it is reset internally and the operation is handled; this is transition-controlled (for
writing once).
The bit is set as

Write_Value_Select

with the specified number (see page 193).

Register 112

SetZero

Register 113

SetTare

Register 114

ResetTare

Register 115

SetTest

Register 116

ResetTest

Register 117

ResetPwf

Register 118

SetFixTare

Register 119

GetFixTare

Register 121

ResetError

To prevent excessively frequent writing in the EAROM memory, the write interval should not be less than
15 seconds.

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