Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 10)

Simulation Environment
Altera performs the following tests on the 40-100GbE MAC and PHY IP core in the simulation environ‐
ment using internal and third party standard bus functional models (BFM):
• Constrained random tests that cover randomized frame size and contents
• Randomized error injection tests that inject Frame Check Sequence (FCS) field errors, runt packets,
and corrupt control characters, and then check for the proper response from the IP core
• Assertion based tests to confirm proper behavior of the IP core with respect to the specification
• Extensive coverage of our runtime configuration space and proper behavior in all possible modes of
operation
Hardware Testing
Altera performs hardware testing of the key functions of the 40-100GbE MAC and PHY IP core. The
Altera hardware tests of the 40-100GbE IP core also ensure reliable solution coverage for hardware related
areas such as synchronization, and reset recovery. The IP core is tested with Stratix IV and Stratix V
devices.
Performance and Resource Utilization
The following sections provide performance and resource utilization data for the 40GbE and 100GbE IP
cores.
Resource Utilization for 40GbE IP Cores
Resource utilization changes if the statistics counters are configured in the IP core. You can specify
whether to include or not include the statistics counters in the 40-100GbE parameter editor, but you
cannot change the setting dynamically.
The 24.24 Gbps variations of the 40-100GbE IP core use the same resources as the standard 40GbE IP
core variations. The 40GBASE-KR4 variations require more resources only for the PHY component.
UG-01088
2014.12.15
Simulation Environment 1-7
About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function Altera Corporation
Send Feedback