Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 6)

40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
The 40- and 100-Gbps Ethernet MAC and PHY IP core offers the following features:
• Parameterizable through the IP Catalog available with the Quartus II software.
• Compliant with the IEEE 802.3ba-2010 High Speed Ethernet Standard available on the IEEE website
(www.ieee.org).
• Soft PCS logic that interfaces seamlessly to Altera 10.3125 Gbps and 25.78125 Gbps serial transceivers.
• Standard XLAUI or CAUI external interface consisting of serial transceiver lanes operating at 10.3125
Gbps, or the CAUI-4 external interface consisting of four serial transceiver lanes operating at
25.78125 Gbps.
• Supports 40GBASE-R4, 100GBASE-R4, and 100GBASE-R10 PHY based on 64B/66B encoding with
data striping and alignment markers to align data from multiple lanes.
• Supports 40GBASE-KR4 PHY and FEC option for interfacing to backplanes
• Supports Synchronous Ethernet (Sync-E)
• Provides CDR recovered clock output signal to the device fabric.
• Optionally accepts two separate input reference clocks for the transmit and receive transceiver
paths.
• Supports a lower–rate 40GbE option at 24.24 Gbps (4 x 6.25 Gbps line rate).
• Ethernet MAC supports the 40GbE or 100GbE line rate with a flexible and configurable feature set.
• Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status
registers.
• Avalon-ST data path interface connects to client logic with the start of frame in the most significant
byte (MSB) when optional adapters are used. Interface has data width 256 or 512 bits depending on the
data rate.
• Optional custom streaming data path interface with narrower bus width and a start frame possible on
64-bit word boundaries without the optional adapters. Interface has data width 128 or 320 bits
depending on the data rate.
• MAC, PHY, or MAC and PHY options configurable at IP generation.
• TX only configuration options, RX only configuration options, and duplex configuration options; the
100GbE CAUI-4 option is available only in duplex mode.
• TX and RX CRC pass-through control.
• RX and TX preamble pass-through option for applications that require proprietary user management
information transfer.
• TX automatic frame padding to meet the 64-byte minimum Ethernet frame length at the 40-100GbE
Ethernet connection.
• Hardware and software reset control.
• TX MAC source address insertion control.
• One MAC address register for configurable RX destination address filtering.
• RX MAC padding removal control.
• Pause frame filtering control.
• Soft error detection on all internal RAMs for high reliability systems.
• RX FIFO in MAC provides cut-through or store-and-forward frame processing.
• Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
UG-01088
2014.12.15
40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1-3
About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function Altera Corporation
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