Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 137)

Table 3-36: MAC Reset Register
Writing a 1’b1 to any of the reset register fields initiates the corresponding reset sequence.
Address Name Bit Description HW
Reset
Value
Access
0x121
MAC Reset
[1] The MAC TX reset register. 1’b0 RW
[0] The MAC RX reset register. 1’b0 RW
Table 3-37: PHY Reset Register
Writing a 1’b1 to any of the reset register fields initiates the corresponding reset sequence.
Address Name Bit Description HW
Reset
Value
Access
0x01d
PHY reset
[2] The PMA reset register. 1’b0 RW
[1] The PCS TX reset register. 1’b0 RW
[0] The PCS RX reset register. 1’b0 RW
Related Information
Resets on page 3-54
3-90 MAC and PHY Reset Registers
UG-01088
2014.12.15
Altera Corporation Functional Description
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