Getting started, Getting started -1 – Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 23

Advertising
background image

Getting Started

2

2014.12.15

UG-01088

Subscribe

Send Feedback

The following sections explain how to install, parameterize, simulate, and initialize the 40-100GbE IP

core:

Installing and Licensing IP Cores

on page 2-2

The 40-100GbE IP core is available with the Quartus II software in the Altera MegaCore IP Library.

Specifying the 40-100GbE IP Core Parameters and Options

on page 2-3

The 40-100GbE IP core supports a standard customization and generation process from the Quartus II IP

Catalog.. This IP core is not supported in Qsys.

IP Core Parameters

on page 2-3

The 40-100GbE parameter editor provides the parameters you can set to configure the 40-100GbE IP core

and simulation testbenches.

Files Generated for the 40-100GbE IP Core

on page 2-10

The Quartus II software version 14.1 generates the following output for your 40-100GbE IP core.

Simulating the IP Core

on page 2-10

Integrating Your IP Core in Your Design

on page 2-11

40-100GbE IP Core Testbenches

on page 2-14

Altera provides a testbench and an example design with most variations of the 40-100GbE IP core. The

testbench is available for simulation of your IP core, and the example design targets a C2 speed grade

device and can be run on hardware. You can run the testbench to observe the IP core behavior on the

various interfaces in simulation.

Simulating the 40-100GbE IP Core With the Testbenches

on page 2-20

Compiling the Full Design and Programming the FPGA

on page 2-24

Initializing the IP Core

on page 2-24

Related Information

Managing Quartus II Projects

Refer to the "Integrating IP Cores" section of this Quartus II Handbook chapter for more information

about generating an Altera IP core and integrating it in your Quartus II project.

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are

trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html

. Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Advertising
This manual is related to the following products: