Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 59)

40GbE IP Core Without Adapters
The following figures illustrate the transmission of a short packet when preamble pass-through is turned
off and when it is turned on.
Figure 3-8: Short Packet Example Without Preamble
Illustrates the transmission of a short packet when preamble pass-through is turned off.
First data
First cycle Second cycle
Destination
MAC addr
Source
MAC Addr
Total
length
Last data
“hello”
Example 3-1: Bus Representation of a Short TX Packet Without Preamble
This example shows the Verilog HDL code that represents the simple packet illustrated in the
previous figure. Note that bit
din_end[5]
in the second cycle, corresponding to the “Last data” in
the figure, is asserted.
wire [6*8-1:0] dst_addr = 48’hffff ffff ffff;
wire [6*8-1:0] src_addr = 48’h0007 edff 1234;
wire [2*8-1:0] len = 16’d64;
\\First cycle:
din = {64'h0, dst_addr, src_addr[47:32]};
din_start = 2'b01;
din_end = 16'b00000000_00000000;
\\Second cycle:
din = {src_addr[31:0], len, "hello", 40'h0};
din_start = 2'b00;
din_end = 16'b00000000_00100000;
3-12 40GbE IP Core Without Adapters
UG-01088
2014.12.15
Altera Corporation Functional Description
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