Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 174)

10GBASE-KR Registers
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2014.12.15
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This appendix duplicates the 10GBASE-KR PHY register listings from the Altera Transceiver PHY IP
Core User Guide . Altera provides this appendix as a convenience to make the full 40GBASE-KR4 register
information available in the 40-100GbE IP core user guide. While Altera makes every attempt to keep the
information in the appendix up-to-date, the most up-to-date information is always found in the Altera
Transceiver PHY IP Core User Guide , and the appendix is not guaranteed to be up-to-date at any
particular time.
Most 40GBASE-KR4 registers are 10GBASE-KR PHY registers of the 10GBASE-KR PHY IP core,
documented in the Altera Transceiver PHY IP Core User Guide and duplicated, with a potential time
lag for updates, in this appendix. The register offsets are identical in the 40GBASE-KR4 variations of the
40-100GbE IP core. However, the 40GBASE-KR4 variations of the 40-100GbE IP core have additional
40GBASE-KR4 related registers and register fields.
40GBASE-KR4 Registers documents the differences between the 10GBASE-KR PHY register definitions
in the 10GBASE-KR PHY Register Defintions section of the Backplane Ethernet 10GBASE-KR PHY IP Core
with FEC Option chapter of the Altera Transceiver PHY IP Core User Guide and the 40GBASE-KR4
registers of the 40-100GbE IP core. All 10GBASE-KR PHY registers and register fields not listed in
40GBASE-KR4 Registers are available in the 40GBASE-KR4 variations of the 40-100GbE IP core.
Where the Altera Transceiver PHY IP Core User Guide and this appendix list 10GBASE-R, substitute
40GBASE-KR4 with auto-negotiation and link training both turned off, and where they list 10GBASE-KR
(except in the description of 0xCB[24:0]), substitute 40GBASE-KR4. Where a register field description in
the Altera Transceiver PHY IP Core User Guide and this appendix refers to link training or FEC in the
single-lane 10GBASE-KR PHY IP core, substitute link training or FEC on Lane 0 of the 40GBASE-KR4 IP
core variation. Where a register field description in the Altera Transceiver PHY IP Core User Guide and
this appendix refers to the Transceiver Reconfiguration IP core, substitute the reconfiguration bundle.
Related Information
Altera Transceiver PHY IP Core User Guide
The 40GBASE-KR4 variations of the 40-100GbE IP core use the 10GBASE-KR PHY IP core PHY registers
at internal offsets 0xB0–0xFF (at IP core register map offsets 0xB0–0xFF), in addition to the registers
listed in 40GBASE-KR4 Registers . Information about this PHY IP core, including up-to-date register
descriptions, is available in the Backplane Ethernet 10GBASE-KR PHY IP Core with FEC Option chapter of
the Altera Transceiver PHY IP Core User Guide..
10GBASE-KR PHY Register Definitions
The Avalon-MM master interface signals provide access to the control and status registers.
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