Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 52)

Related Information
MAC Address Registers on page 3-107
Includes information about the
MADDR_CTRL
,
SRC_AD_LO
, and
SRC_AD_HI
registers.
Length/Type Field Processing
This two-byte header represents either the length of the payload or the type of MAC frame. When the
value of this field is equal to or greater than 1536 (0x600) it indicates a type field. Otherwise, this field
provides the length of the payload data that ranges from 0–1500 bytes. The TX MAC does not modify this
field before forwarding it to the network.
Frame Padding
When the length of client frame is less than 64 bytes (meaning the payload is less than 46 bytes), the TX
MAC module inserts pad bytes (0x00) after the payload to create a frame length equal to the minimum
size of 64 bytes.
Frame Check Sequence (CRC-32) Insertion
The TX MAC computes and inserts a CRC32 checksum in the transmitted MAC frame. The frame check
sequence (FCS) field contains a 32-bit CRC value. The MAC computes the CRC32 over the frame bytes
that include the source address, destination address, length, data, and pad. The CRC checksum computa‐
tion excludes the preamble, SFD, and FCS. The encoding is defined by the following generating
polynomial:
FCS(X) = X32 +X26 +X23 +X22 +X16 +X12 +X11 +X10 +X8 +X7 +X5 +X4 +X2 +X1 +1
CRC bits are transmitted with MSB (X32) first.
Independent user configuration register bits control FCS CRC insertion at runtime. Bit [0] of the
CRC_CONFIG
register enables and disables CRC insertion. By default, the CRC insertion feature is enabled.
Related Information
• Order of Transmission on page 3-16
Illustrations of the byte order and octet transmission order on the Avalon-ST client interface.
• CRC Configuration Register on page 3-105
Information about the
CRC_CONFIG
register.
Inter‑Packet Gap Generation and Insertion
The TX MAC maintains the minimum inter-packet gap (IPG) between transmitted frames required by
the IEEE 802.3 Ethernet standard. The standard requires an average minimum IPG of 96 bit times (or 12
byte times). The deficit idle counter maintains the average IPG of 12 bytes.
The MAC adjusts the IPG to compensate for Alignment Marker insertion by the PHY. You can program
this adjustment using the
IPG_DEL_PERIOD
and
IPG_DEL_ENABLE
registers at offsets 0x126 and 0x127,
respectively. By default, the adjustment removes one Idle byte for every 16384 bytes. This removal rate
corresponds to the bandwidth used by the Alignment Marker that the PHY inserts in the outgoing
Ethernet communication. You can modify the value in the
IPG_DEL_PERIOD
register to specify more or
less frequent removal of Idle bytes from the sequence.
UG-01088
2014.12.15
Length/Type Field Processing 3-5
Functional Description Altera Corporation
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