Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 91)

Table 3-12: Lane to Lane Deskew Interface Signals
Signal Name Direction Description
lanes_deskewed Input Indicates lane to lane skew is
corrected. Available as an input
to the 40-100GbE MAC IP core
only.
lanes_deskewed Output Indicates lane to lane skew is
corrected. Available as an output
from the 40-100GbE PHY IP
core and the 40-100GbE MAC
and PHY IP core.
PCS Test Pattern Generation and Test Pattern Check
The PCS can generate a test pattern and detect a scrambled idle test pattern. PCS test-pattern mode is
suitable for receiver tests and for certain transmitter tests.
When bit 0 of the
TEST_MODE
register at offset 0x019 has the value of 1, a scrambled idle pattern is
enabled. In this mode, the scrambler generates a test pattern. The scrambler does not require seeding
during test-pattern operation. The input to the scrambler is a control block (blocktype=0x1E). The TX
PCS adds synchronous headers and alignment markers to the data stream, enabling the RX PCS to align
and deskew the PCS lanes.
For information about the definition of idle test patterns, refer to Figure 82–5—64B/66B block formats
illustrated in the IEEE 802.3ba 2010 100G Ethernet Standard.
Figure 3-31: PCS Test Pattern Generation
tx_test_en
mii_c[39:0] (100 GB) or mii_c[15:0] (40 GB)
Normal mii Control Signals
40’HFF_FFFF_FFFF (100 GB) or
16’HFFFF (40 GB)
MII Control
MII Data
mii_d[319:0] (100 GB) or mii_d[127:0] (40 GB)
Normal mii Control Signals
320’H07070707...07 (100 GB) or
128’HFFFF0707...07 (40 GB)
tx_test_en
The scrambled idle test-pattern checker utilizes the block lock state diagram, the alignment marker state
diagram, the PCS deskew state diagram, and the descrambler; these blocks operate as if in normal data
reception. The bit error rate (BER) monitor state diagram is disabled during RX test-pattern mode. When
3-44 PCS Test Pattern Generation and Test Pattern Check
UG-01088
2014.12.15
Altera Corporation Functional Description
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