Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 27)

Parameter Type Range Default Setting Parameter Description
PHY reference
frequency (2)
Integer
(encodi
ng)
The range and default settings depend
on the PHY configuration.
Despite its apparent availability in the
parameter editor, CAUI–4 variations
do not support the 322.265625 MHz
clock frequency. For correct
functioning of CAUI–4 variations, you
must set this parameter to the value of
644.53125 MHz.
Sets the expected incoming PHY
clk_ref
reference frequency. The
input clock frequency must match
the frequency you specify for this
parameter.
In Sync-E variations, the input clock
frequencies for the
rx_ref_clk
and
tx_ref_clk
clocks must match the
frequency you specify for this
parameter, although the two clocks
can be driven from different sources
and need not be aligned with each
other.
Advanced Design Options
Status clock
rate (2)
Float • Stratix IV:
37.5–50.0
• Arria V GZ or
Stratix V:
100.0–125.0
• Stratix IV: 37.5
• Arria V GZ or
Stratix V: 100.0
Sets the clock rate of
clk_status
in
MHz.
Statistics
counters (5)
Boolean • True
• False
True If turned on, the IP core includes
built–in statistics counters. If turned
off, the IP core is configured without
statistics counters.
Enable SyncE
support
Boolean • True
• False
False Enables or disables a separate
reference clock for the RX CDR
block in the transceiver and exposes
the RX recovered clock as an output
signal. If this option is turned on
(set to true), the TX PLL and the RX
CDR in the transceiver have
separate input reference clocks and
the RX recovered clock is visible as
an IP core output signal. If it is
turned off, the two PLLs share one
input reference clock and the RX
recovered clock is not available as an
output signal.
UG-01088
2014.12.15
IP Core Parameters 2-5
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