Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 195
Date
ACDS
Version
Changes
• If you are transitioning from an earlier version of the IP core, you must
complete the following steps:
• Generate the 12.1 release from the MegaWizard Plug-In Manager
into a new project directory; this will generate a .qip file to include in
the Quartus II software project, along with the required Verilog HDL
files. For more information, refer to “Getting Started” on page 2–1.
• Quartus II software assignments from previous releases that
reference the internal IP hierarchy (such as logic lock regions) must
be updated for changes in the internal hierarchy. Hierarchy changes
include the following:
• The top-level Verilog in the synthesis file set has one level below it
named <name of your IP instance>_inst. All further instances
begin under the <name of your IP instance>_inst directory.
• The
pcs_tx
,
pcs_rx
, and
phy_csr
instances now reside under
phy/phy_pcs
• The
pcs_tx
,
pcs_rx
, and
phy_csr
instances now reside under
phy/phy_pcs
• Nodes for the Stratix V device PMA now reside under phy/pma/
pma_bridge
• Generate example designs from the 12.1 release of the MegaWizard
Plug-In Manager for a complete set of new Quartus II software
assignments
• The reconfiguration controller must be instantiated and connected to
the IP core. For more information, refer to “External Reconfiguration
Controller” on page 3–26 and “12.1 Example Design” on page A–1
• Note the
GXB_0PPM_CORECLK
and
GXB_0PPM_CORE_CLOCK
Quartus II
software settings are no longer required.
• Feature additions:
• 40GbE Lower Rate 24.24 Gbps MAC and PHY
• 100GbE CAUI–4 PHY
• RX Automatic Pad Removal Control
• Pause Control Frames Filtering Control
• Updated or added signals:
• Top-level output and input high-speed serial lines from the
transceivers
• External reconfiguration controller
• TX MAC to PHY connections
• RX MAC to PHY connections
• Added registers:
• PAD_CONFIG at offset 0x124
• Low Latency PHY IP Core registers for CAUI–4 at offsets 0x800–
0x9FF, 0xA00–0xBFF, 0xC00–0xDFF, and 0xE00–0xFFF.
D-6
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
UG-01088
2014.12.15
Altera Corporation
Additional Information