Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 49)

High Level System Overview
Figure 3-1: 40GbE and 100GbE MAC and PHY MegaCore Function
Main block, internal connections, and external block requirements.
40- or 100-Gbps Ethernet MAC and PHY MegaCore Function
TX
FIFO
TX
MAC
RX
MAC
40- or 100-GbE MAC
PMA
PMA PCS
PHY
TX
Adapter
PCS
XLGMII w/data_valid signal
or CGMII w/data_valid signal
4 x 40 bits or
10 x 40 bits
XLAUI: 4 x 10.3125 Gbps or
CAUI: 10 x 10.3125 Gbps
CAUI-4: 4 x 25.78125 Gbps
Custom Streaming
Avalon-ST
Avalon-ST
Control and
Status Interface
Avalon-MM
Avalon-MM
RX
Adapter
Custom Streaming
Reconfiguration
Controller
40-100GbE MAC and PHY Functional Description
The Altera 40-100GbE IP core implements the 40-100GbE Ethernet MAC in accordance with the IEEE
802.3ba 2010 40G and 100G Ethernet Standard. This IP core handles the frame encapsulation and flow of
data between a client logic and Ethernet network via a 40-100GbE Ethernet PCS and PMA (PHY).
In the transmit direction, the MAC accepts client frames, and inserts inter-packet gap (IPG), preamble,
start of frame delimiter (SFD), header, padding, and checksum bits before passing them to the PHY. The
PHY encodes the MAC frame as required for reliable transmission over the media to the remote end.
In the receive direction, the PHY passes frames to the MAC. The MAC accepts frames from the PHY,
performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of
the frame to the client. In RX preamble pass-through mode, the MAC passes on the preamble and SFD to
the client instead of stripping them out.
3-2 High Level System Overview
UG-01088
2014.12.15
Altera Corporation Functional Description
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