Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 75

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40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)

The RX bus without adapters consists of five 8-byte words, or 320 bits, operating at a frequency above

315 MHz for the 100GbE IP core or two 8-byte words, or 128 bits, for the 40GbE IP core, nominally at

315 MHz. This bus drives data from the RX MAC to the RX client.

Figure 3-25: RX MAC to Client Interface Without Adapters

The custom streaming interface bus width varies with the IP core variation. In the figure, <w> = 2 for the

40GbE IP core and <w> = 5 for the 100GbE IP core.

RX Client

Logic

RX MAC

dout_d[<w>*64-1:0]

dout_c[<w>*8-1:0]

dout_first_data[<w>-1:0]

dout_last_data[<w>*8-1:0]

dout_payload[<w>-1:0]

dout_runt_last_data[<w>-1:0]

dout_fcs_error

dout_fcs_valid

dout_dst_addr_match[<w>-1:0]

dout_valid

clk_rxmac

Table 3-6: Signals of the RX Client Interface Without Adapters

In the table, <w> = 2 for the 40GbE IP core and <w> = 5 for the 100GbE IP core.

Signal Name

Direction

Description

dout_d[<w>*64-

1:0]

Output

Received data and Idle bytes. In RX preamble pass-through mode, this

bus also carries the preamble.

dout_c[<w>*8-

1:0]

Output

Indicates control bytes on the data bus. Each bit of dout_c indicates

whether the corresponding byte of

dout_d

is a control byte. A bit is

asserted high if the corresponding byte on

dout_d

is an Idle byte or the

Start byte, and has the value of zero if the corresponding byte is a data

byte or, in preamble pass-through mode, a preamble or SFD byte.

dout_first_

data[<w>-1:0]

Output

Indicates the first data word of a frame, in the current

clk_rxmac

cycle.

In RX preamble pass-through mode, the first data word is the word

that contains the preamble. When the RX preamble pass-through

feature is turned off, the first data word is the first word of Ethernet

data that follows the preamble.

dout_last_

data[<w>*8–1:0]

Output

Indicates the final data byte of a frame, before the FCS, in the current

clk_rxmac

cycle.

3-28

40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)

UG-01088

2014.12.15

Altera Corporation

Functional Description

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