Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 150)

Addr Name Bit Description HW Reset
Value
Access
0x113
RECEIVE_
PAUSE_
CONTROL
[9] When set to 1, enables unicast pause receive. 1’b0 RW
[8] When set to 1, enables multicast pause
receive.
1’b0 RW
[7:0] Pause quantum time configuration as follows:
• 1
pause_quanta
= 512 bit times
• For 40Gbps, 1
pause_quanta
is 12.8 ns
• For 100Gbps, 1
pause_quanta
is 5.12 ns
•
pause_quantum_delta = 256 × Tclk /
Tpause_quanta
For example: 40 Gbps, clk =315 MHz, Tclk =
3.2ns,
pause_quantum_delta
=
round(256*(3.2/12.8)) = 64.
0x00000000 RW
0x114
INSERT_
PAUSE_
CONTROL
[16] When set to 1, sends a multicast pause
request. When set to 0, sends a unicast pause
request.
1’b0 RW
[15:0] Specifies the pause time. A non-zero value
specifies an XON. Zero specifies XOFF.
0x0000 RW
0x115
TX_PAUSE_
DST_ADDR_
LSB
[31:0] Destination address LSB. 0x00000000 RW
0x116
TX_PAUSE_
DST_ADDR_
MSB
[31:0] Destination address MSB. 0x00000000 RW
0x117 INSERT_
PAUSE
[31:0] Any write to this address triggers a pause
packet insertion into the TX data stream.
Other pause registers, described in this table,
specify the properties of this pause packet.
0x00000000 W
Related Information
Pause Control and Generation Interface on page 3-35
Describes the pause signals available in 40-100GbE IP core variations that include a MAC with a custom
streaming client interface.
UG-01088
2014.12.15
Pause Registers 3-103
Functional Description Altera Corporation
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