Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 193
Date
ACDS
Version
Changes
June 2013
1.3(v13.0
software
release)
• Updated for use with version 13.0 of the Quartus II software and the
MegaWizard Plug-In Manager.
• Added preamble pass-through option. This change affects various
sections in “TX Datapath” on page 3–5 and “RX Datapath” on page 3–
20, and includes the addition of a new
Preamble Pass-Through
Configuration
register (offset 0x125), described in “MAC Feature
Configuration Registers” on page 3–62.
• Added transmitter average inter-packet gap (IPG) adjustment option.
This change affects “Inter-Packet Gap Generation and Insertion” on
page 3–7 and includes the addition of two new registers (
IPG_DEL_
PERIOD
at offset 0x126 and
IPG_DEL_ENABLE
at offset 0x127), described
in “R**MAC Feature Configuration Registers” on page 3–62.
• Added new section “MAC Feature Configuration Registers” on page 3–
62 for the new registers. Moved the description of the
CRC_CONFIG
register (offset 0x123) to this new section.
• Reorganized Chapter 2, Getting Started to remove non-IP core specific
information.
• Moved instructions for IP core initialization from “Software Interface:
Registers” to new section “Initializing the IP Core” on page 2–30.
• Updated resource utilization numbers in “Performance and Resource
Utilization” on page 1–5.
• Clarified device speed grades per device family variant, in “Device Speed
Grade Support” on page 1–4.
• Clarified definitions of cut-through, store and forward, and
promiscuous receive modes, in “40-100GbE IP Core Modes of
Operation” on page 3–34.
• Clarified destination address checking controls in “Address Checking ”
on page 3–22 and in “MAC Address Registers” on page 3–64.
• Removed Appendix B, Address Map Changes for 12.1, and moved
information to Document Revision History entry for Quartus II
software v12.1 release. The update added registers but did not change
register names or offsets of existing registers.
• Fixed descriptions of allowed transceiver reference clock frequencies
and PCS clock frequencies:
• Clarified that 644 MHz is not an allowed frequency for CAUI–4
variations, despite its presence in the parameter editor as an
apparently allowed value for the PHY Reference Frequency
parameter.
• Provided correct PCS clock frequency for CAUI–4 variations.
• Provided correct frequencies for 24.24 Gbps variations.
• Modified “100GbE IP Core without Adapters” on page 3–14 to clarify
that only two SOPs can occur on the TX custom streaming client
interface during the same clock cycle.
• Added instructions for using the example design in Appendix A, 13.0
Example Design.
• Improved descriptions of various signals and fixed typos.
D-4
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
UG-01088
2014.12.15
Altera Corporation
Additional Information