Related information – Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 114

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Figure 3-34: Top-Level Signals of the 40-100GbE IP Core with Adapters

Ethernet Top-Level Signals with Adapters

MAC and PHY

Asynchronous

Reset Signals

Avalon-MM

Control

and Status

Link Fault

Signaling

TX MAC to PHY

Connections

RX MAC to PHY

Connections

mac_rx_arst_ST

mac_tx_arst_ST

pcs_rx_arst_ST

pcs_tx_arst_ST

pma_arst_ST

status_addr [15:0]

status_read

status_write

status_writedata [31:0]

status_readdata [31:0]

status_readdata_valid

tx_mii_d [(64 x <w>)-1:0]

tx_mii_c [(8 x <w>)-1:0]

tx_mii_valid

tx_mii_ready

tx_lanes_stable

rx_mii_d [(64 x <w>)-1:0]

rx_mii_c [(8 x <w>)-1:0]

rx_mii_valid

Transceiver Serial

Data <v> lanes

@ 10.3125 Gbps or

25.78125 Gbps

Increment Vectors of

Statistics Counters

(only used internally

when in duplex mode)

Pause Status Signaling

(only used internally

when in duplex mode)

lanes_deskewed

lanes_deskewed

Lane to Lane

Deskew

TX MAC to PHY

Connections

RX MAC to PHY

Connections

tx_mii_d [(64 x <w>)-1:0]

tx_mii_c [(8 x <w>)-1:0]

tx_mii_valid

tx_mii_ready

tx_lanes_stable

rx_mii_d [(64 x <w>)-1:0]

rx_mii_c [(8 x <w>)-1:0]

rx_mii_valid

TX Avalon-ST

Interface

RX Avalon-ST

Interface

l<n>_tx_data[(64 x < n>)-1:0]

l<n>_tx_empty[< l>-1:0]

l<n>_tx_startofpacket

l<n>_tx_endofpacket

l<n>_tx_ready

l<n>_tx_valid

l<n>_rx_data[(64 x <n>)-1:0]

l<n>_rx_empty[<l>-1:0]

l<n>_rx_startofpacket

l<n>_rx_endofpacket

l<n>_rx_error

l<n>_rx_valid

l<n>_rx_fcs_valid

l<n>_rx_fcs_error

Clocks

clk_txmac

clk_rxmac

clk_status

clk_ref

tx_clk_ref

rx_clk_ref

rx_recovered_clk

External Reconfiguration

Controller for Arria V GZ

and Stratix V Devices

External Reconfiguration

Controller for 100GbE

CAUI-4 Configurations Only

(duplex mode only)

(replace clk_ref

in Sync-E variations)

(Sync-E variations only)

KR4 Microprocessor

Interface for

40GBASE-KR4

Microprocessor-Enabled

Configurations Only

v>-1:0]

v>-1:0]

rx_serial [<

tx_serial [<

v>)-1:0]

v>)-1:0]

v>)-1:0]

v>)-1:0]

pause_match_from_rx

pause_time_from_rx [15:0]

pause_match_to_tx

pause_time_to_tx [15:0]

remote_fault_from_rx

local_fault_from_rx

remote_fault_to_tx

local_fault_to_tx

remote_fault_status

local_fault_status

rx_statistic_counters[22:0]

tx_statistic_counters[21:0]

reconfig_to_xcvr[(140 x <

reconfig_to_xcvr[(70 x <

reconfig_from_xcvr[(92 x <

reconfig_from_xcvr[(46 x <

reconfig_to_xcvr0[209:0]

reconfig_to_xcvr1[209:0]

reconfig_to_xcvr2[209:0]

reconfig_to_xcvr3[209:0]

reconfig_from_xcvr0[137:0]

reconfig_from_xcvr1[137:0]

reconfig_from_xcvr2[137:0]

reconfig_from_xcvr3[137:0]

upi_mode_en[3:0]

upi_adj[7:0]

upi_inc[3:0]

upi_dec[3:0]

upi_pre[3:0]

upi_init[3:0]

upi_st_bert[3:0]

upi_train_err[3:0]

upi_lock_err[3:0]

upi_rx_trained[3:0]

upo_cm_done[3:0]

upo_bert_done[3:0]

upo_ber_cnt[47-1:0]

upo_ber_max[3:0]

upo_coef_max[3:0]

upo_enable[3:0]

upo_frame_lock[3:0]

rc_busy[3:0]

lt_start_rc[3:0]

main_rc[23:0]

post_rc[19:0]

pre_rc[15:0]

tap_to_upd[11:0]

seq_start_rc[3:0]

dfe_start_rc[3:0]

dfe_mode[7:0]

ctle_start_rc[3:0]

pcs_mode_rc[5:0]

en_lcl_rxeq[3:0]

rxeq_done[3:0]

reco_mif_done

ctle_rc[15:0]

ctle_mode[7:0]

Legend:

Black = Included in all IP cores.

Blue

= Included in 40-100GbE (alt_e*.v)

and 40-100GbE MAC (alt_e*_mac.v)

Purple

= Included in 40-100GbE (alt_e*.v)

and 40-100GbE PHY (alt_e*_phy.v)

Green

= Included only in 40-100GbE MAC

(alt_e*_mac.v)

Dark Grey

= Included only in 40-100GbE PHY

(alt_e*_phy.v)

Reconfiguration

Interface for

40GBASE-KR4

Reconfiguration-Enabled

Configurations Only

Link Training

Interface for

40GBASE-KR4

Link Training-Enabled

Configurations Only

RX Equalization

Interface for

40GBASE-KR4

RX Equalization-Enabled

Configurations Only

pause_insert_tx

pause_insert_time [15:0]

pause_insert_mcast

pause_insert_dst [47:0]

pause_insert_src [47:0]

Pause Control

and Generation

Related Information

Signals of MAC and PHY Variations Without Adapters

on page 3-55

Signals in variations with adapters are the same as signals in variations without adapters on most

interfaces. The only exceptions are the RX and TX client interfaces (completely different).

40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)

on page 3-6

Describes the TX client interface in IP core variations with adapters.

40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface)

on page 3-25

Describes the RX client interface in IP core variations with adapters.

UG-01088

2014.12.15

Signals of MAC and PHY Variations With Adapters

3-67

Functional Description

Altera Corporation

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