Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 3)

40-100GbE IP Core TX Datapath..................................................................................................3-3
40-100GbE IP Core TX Data Bus Interfaces................................................................................ 3-6
40-100GbE IP Core RX Datapath................................................................................................3-20
40-100GbE IP Core RX Data Bus Interfaces..............................................................................3-25
40GbE Lower Rate 24.24 Gbps MAC and PHY.........................................................................3-32
100GbE CAUI–4 PHY.................................................................................................................. 3-32
External Reconfiguration Controller.......................................................................................... 3-32
Congestion and Flow Control Using Pause Frames................................................................. 3-33
Pause Control and Generation Interface....................................................................................3-35
Pause Control Frame and Non-Pause Control Frame Filtering and Forwarding................ 3-36
40-100GbE IP Core Modes of Operation .................................................................................. 3-37
Link Fault Signaling Interface...................................................................................................... 3-37
Statistics Counters Interface.........................................................................................................3-39
MAC – PHY XLGMII or CGMII Interface................................................................................3-42
Lane to Lane Deskew Interface.................................................................................................... 3-43
PCS Test Pattern Generation and Test Pattern Check............................................................. 3-44
Transceiver PHY Serial Data Interface....................................................................................... 3-45
40GBASE-KR4 IP Core Variations............................................................................................. 3-46
Control and Status Interface.........................................................................................................3-51
Clocks.............................................................................................................................................. 3-51
Resets............................................................................................................................................... 3-54
Signals..........................................................................................................................................................3-55
Signals of MAC and PHY Variations Without Adapters.........................................................3-55
Signals of MAC and PHY Variations With Adapters...............................................................3-66
Signals of 40-100GbE MAC-Only IP Core Variations............................................................. 3-68
Signals of 40-100GbE PHY-Only IP Core Variations...............................................................3-72
Software Interface: Registers.................................................................................................................... 3-76
40-100GbE IP Core Registers.......................................................................................................3-79
40-100GbE Example Design Registers......................................................................................3-116
Ethernet Glossary.....................................................................................................................................3-119
Debugging the 40GbE and 100GbE Link............................................................4-1
40-100GbE IP Core Example Design................................................................. A-1
Address Map Changes for the 40-100GbE IP Core v12.0 Release..................... B-1
10GBASE-KR Registers...................................................................................... C-1
10GBASE-KR PHY Register Definitions.................................................................................................C-1
Additional Information..................................................................................... D-1
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History
..................................................................................................................................................................D-1
How to Contact Altera............................................................................................................................... D-9
Typographic Conventions......................................................................................................................... D-9
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide TOC-3
Altera Corporation