Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 92)

align_status
is true and the scrambled idle RX test-pattern mode is active, the scrambled idle test-
pattern checker observes the synchronous header and the output from the descrambler. When the
synchronous header and the output of the descrambler is an idle pattern, a match is detected. When
operating in scrambled idle test pattern, the test-pattern error counter counts blocks with a mismatch.
Any mismatch indicates an error and shall increment the test-pattern error counter.
The test-pattern check uses the following register fields:
1. Bit 1 of the
TEST_MODE
register at offset 0x019 enables the RX test-pattern mode.
2. The
TEST_PATTERN_COUNTER
register at offset 0x01A , a 32-bit register that saturates, counts the
number of mismatched blocks when the IP core is in test-pattern mode.
3. Bit 2 of the
TEST_MODE
register enables software to clear the test-pattern error counter.
Related Information
• Test Mode Register on page 3-88
Information about the
TEST_MODE
register.
• Test Pattern Counter Register on page 3-88
Information about the
TEST_PATTERN_COUNTER
register.
• IEEE website
The IEEE 802.3ba-2010 100G Ethernet Standard is available on the IEEE website.
Transceiver PHY Serial Data Interface
The core uses a 40-bit ×<n> lane digital interface to send data to the TX high-speed serial I/O pins
operating at 10.3125 Gbps in the standard 40GbE and 100GbE variations, at 6.25 Gbps in the 24.24
variations, and at 25.78125 Gbps in the CAUI–4 variations. The
rx_serial
and
tx_serial
ports connect
to the 10.3125 Gbps, 6.25 Gbps, or 25.78125 Gbps pins. The protocol includes automatic reordering of
serial lanes so that any ordering is acceptable. Virtual lanes 0 and 1 transmit data on
tx_serial[0]
.
PCS BER Monitor
The PCS implements bit error rate (BER) monitoring as specified by the IEEE 802.3ba-2010 100G
Ethernet Standard. When the PCS deskews the data and aligns the lanes, the BER monitor checks the
signal quality and asserts
hi_ber
if it detects excessive errors. When
align_status
is asserted and
hi_ber
is deasserted, the RX PCS continuously accepts blocks and generates RXD <63:0> and RXC <7:0> on the
XLGMII or CGMII interface.
High BER occurs when 97 invalid 66-bit synchronous headers are detected for 100GbE within 500 µs or
detected for 40GbE within 1.25 ms. When fewer than 97 invalid 66-bit synchronous headers occur in the
same window, the IP core exists the high BER state.
For more information, refer to Figure 82–13—BER monitor state diagram illustrated in the IEEE
802.3ba-2010 100G Ethernet Standard.
Related Information
IEEE website
The IEEE 802.3ba-2010 100G Ethernet Standard is available on the IEEE website.
UG-01088
2014.12.15
Transceiver PHY Serial Data Interface 3-45
Functional Description Altera Corporation
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