Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 94)

Related Information
Altera Transceiver PHY IP Core User Guide
The 40GBASE-KR4 variations of the 40-100GbE IP core use the Altera 10GBASE-KR PHY IP core.
Information about this PHY IP core, including functional descriptions of the listed features, is available in
the Backplane Ethernet 10GBASE-KR PHY IP Core with FEC Option chapter of the Altera Transceiver
PHY IP Core User Guide. In this chapter, functional descriptions of the FEC, AN, and LT features are
available in the "Forward Error Correction (Clause 74)", "Auto Negotiation (AN), Clause 73", and "Link
Training (LT), Clause 72" sections, respectively.
40GBASE-KR4 Reconfiguration Interface
The 40GBASE-KR4 reconfiguration interface supports low-level control of analog transceiver properties
for link training and auto-negotiation in the absence of a predetermined environment for the IP core.
Table 3-13: 40GBASE-KR4 Reconfiguration Interface Signals
Signals with a width of 4 x n are divided into fields of width n. Bits [n-1:0] refer to Lane 0, bits [2n-1:n] refer to
Lane 1, bits [3n-1:2n] refer to Lane 2, and bits [4n-1:3n] refer to Lane 3. You can use these signals to dynamically
change between auto-negotiation, link training, and normal data modes.
Note that the regular Stratix V dynamic reconfiguration interface, the
reconfig_from_xcvr
,
reconfig_to_xcvr
,
and
reconfig_busy
signals, are also available in 40GBASE-KR4 IP core variations. The reconfiguration bundle in
the example design includes the Altera Transceiver Reconfiguration Controller. For an example of how to
coordinate dynamic transceiver reconfiguration using these two interfaces, the regular Stratix V transceiver
reconfiguration interface and the 40GBASE-KR4 specific interface, refer to the example design reconfiguration
bundle.
Signal Name Direction Description
rc_busy[3:0] Input When asserted, indicates that reconfiguration is in progress.
lt_start_rc[3:0] Output When asserted, starts the TX PMA equalization reconfigu‐
ration on the corresponding lane. This signal is present only
if link training is enabled.
main_rc[23:0] Output The main TX equalization tap value, which is the same as
V
OD
. This signal is present only if link training is enabled.
post_rc[19:0] Output The post-cursor TX equalization tap value for the
corresponding lane. This signal is present only if link
training is enabled.
pre_rc[15:0] Output The pre-cursor TX equalization tap value for the
corresponding lane. This signal is present only if link
training is enabled.
UG-01088
2014.12.15
40GBASE-KR4 Reconfiguration Interface 3-47
Functional Description Altera Corporation
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