Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 44
The successful testbench run displays the following output:
#
# *****************************************
# ** 40g Ethernet Testbench
# **
# **
# ** Target Device: Stratix V
# ** IP Configuration: 40 Gbe
# ** Variant Name: abc
# ** Status Clock Rate: 100000 KHz
# ** Statistics Registers: Enabled
# **
# ** This variant is MAC & PHY
# ** Interface: Avalon-ST
# *****************************************
# ** Reseting the IP Core...
# **
# **
# *****************************************
# ** Waiting for alignment and deskew...
# **
# **
# ** Virutal lane locked: None (lanes left: 4) |@@@@|
# All lanes locked. Starting deskew at time 5528000
# ** Virtual lane locked: 0 (lanes left: 3) |@@@\|
# ** Virtual lane locked: 1 (lanes left: 2) |@@/\|
# ** Virtual lane locked: 2 (lanes left: 1) |@\/\|
# ** Virtual lane locked: 3 (lanes left: 0) |/\/\|
# Deskew complete at time 6404800
# ** All virtual lanes locked and deskewed, ready for data |----|
# *****************************************
# ** Starting TX traffic...
# **
# **
# ** Sending Packet 1...
# ** Sending Packet 2...
# ** Sending Packet 3...
# ** Sending Packet 4...
# ** Sending Packet 5...
# ** Sending Packet 6...
# ** Sending Packet 7...
# ** Sending Packet 8...
# ** Sending Packet 9...
# ** Sending Packet 10...
# ** Received Packet 1...
# ** Received Packet 2...
# ** Received Packet 3...
# ** Received Packet 4...
# ** Received Packet 5...
# ** Received Packet 6...
# ** Received Packet 7...
# ** Received Packet 8...
# ** Received Packet 9...
# ** Received Packet 10...
# **
# ** Testbench complete.
# **
# *****************************************
# ** Note: $finish : ./alt_40gbe_tb.v(181)
# Time: 7490400 ps Iteration: 0 Instance: /alt_40gbe_tb
2-22
Testbench Output Example: 40GbE IP Core with Adapters
UG-01088
2014.12.15
Altera Corporation
Getting Started