Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 32)

• 40-100GbE IP Core Testbenches on page 2-14
Provides a list of IP core variations (parameter value choices) for which the Quartus II software can
generate a testbench and example design if you turn on Generate example design.
Files Generated for the 40-100GbE IP Core
The Quartus II software version 14.1 generates the following output for your 40-100GbE IP core.
Figure 2-2: IP Core Generated Files
Notes:
1. If generated for your IP variation
<Project Directory>
<your_ip>_sim
<simulator_vendor >
<simulator setup scripts>
<your_ip>.qip - Quartus II IP integration file
<your_ip>.sip - Lists files for simulation
<your_ip> _example - Testbench and example project1
<your_ip>.v, .sv, or .vhd - Top-level IP synthesis file
<tyour_ip>.v
<your_ip>_syn.v or .vhd - Timing & resource estimation netlist1
<your_ip>.cmp - VHDL component declaration file
<your_ip>.bsf - Block symbol schematic file
<your_ip> - IP core synthesis files
<your_ip>.sv, .v, or .vhd - HDL synthesis files
<your_ip>.sdc - Timing constraints file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.spd - Combines individual simulation scripts
<your_ip>_sim.f - Refers to simulation models and scripts
Simulating the IP Core
You can simulate your 40GbE or 100GbE IP core variation with the functional simulation model and the
testbench or example design generated with the IP core. The functional simulation model is a cycle-
accurate model that allows for fast functional simulation of your IP core instance using industry-standard
VHDL or Verilog HDL simulators. If your IP core variation does not generate a matching testbench, you
can create your own testbench to exercise the IP core functional simulation model.
The functional simulation model and testbench files are generated in project subdirectories. These
directories also include scripts to compile and run the example design.
Note: Use the simulation models only for simulation and not for synthesis or any other purposes. Using
these models for synthesis creates a nonfunctional design.
2-10 Files Generated for the 40-100GbE IP Core
UG-01088
2014.12.15
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