Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 89)

Name Signal
Direction
Description
rx_inc_fcs_err Output Asserted for one cycle when a RX packet with FCS errors is received.
Assertion of this signal might be early or delayed compared to
assertion of the
dout_fcs_error
signal on the RX custom streaming
interface, because the IP core asserts
rx_inc_fcs_err
when the MAC
sees the FCS error, and asserts
dout_fcs_error
when it presents the
relevant frame on the custom streaming client interface. Depending on
the filtering settings in the
RX_FILTER_CTRL
register, the frame might
not appear at all on the client interface.
rx_inc_fragment Output Asserted for one cycle when a RX frame less than 64 bytes and
reporting a CRC error is received.
rx_inc_jabber Output Asserted for one cycle when an oversized RX frame reporting a CRC
error is received.
rx_inc_sizeok_
fcserr
Output Asserted for one cycle when a valid RX frame with FCS errors is
received.
Related Information
Statistics Registers on page 3-108
The statistics status bit output vectors are provided whether you select the statistics counters module
option or not. The increment vectors are brought to the top level as output ports and function as input
ports to the control and status registers (CSR).
MAC – PHY XLGMII or CGMII Interface
The PHY side of the MAC implements the XLGMII or CGMII protocol as defined by the IEEE 802.3ba
standard. The standard XLGMII or CGMII implementation consists of 32 bit wide data bus. However, the
Altera implementation uses a wider bus interface in connecting a MAC to the internal PHY. The width of
this interface is 320 bits for the 100GbE IP core and 128 bits for the 40GbE IP core.
Table 3-10: XL/CGMII Permissible Encodings
Lists XL/CGMII permissible encodings. Memorizing a few of the XL/CGMII encodings greatly facilitates
understanding of Ethernet waveforms. The XL/CGMII encodings are backwards compatible with older Ethernet
and have convenient mnemonics. The
DATAPATH_OPTION
RTL parameter instantiates TX and RX backwards
compatibility and is set by default.
Control Data Description
0 xx Packet data, including preamble and FCS bytes.
1 07 Idle.
1 fb Start of Frame (fb = frame begin).
3-42 MAC – PHY XLGMII or CGMII Interface
UG-01088
2014.12.15
Altera Corporation Functional Description
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