Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 122
The following 40-100GbE MAC and PHY IP core signals are available in PHY-only IP core variations:
• Clock signals:
•
clk_ref
(relevant only for IP core variations with the Sync–E support option turned off)
•
tx_clk_ref
(relevant only for IP core variations with the Sync–E support option turned on)
•
rx_clk_ref
(relevant only for IP core variations with the Sync–E support option turned on)
•
rx_recovered_clk
(relevant only for IP core variations with the Sync–E support option turned on)
•
clk_rxmac
•
clk_txmac
• PCS and PMA reset signals:
•
pcs_tx_arst_ST
•
pcs_rx_arst_ST
•
pma_arst_ST
• Control and status interface signals to access PHY component registers.
• Ethernet link signals
tx_serial
and
rx_serial
.
• PHY output status signals
tx_lanes_stable
and
lanes_deskewed
.
• Signals to connect to the external transceiver reconfiguration controller (relevant for Arria V GZ and
Stratix V devices only).
• 40GBASE-KR4 microprocessor interface and reconfiguration interface signals.
The remaining 40-100GbE MAC and PHY IP core signals are associated with the MAC and are not
available in PHY-only IP core variations.
Table 3-22: 40-100GbE PHY IP Core Signals Not Visible in 40-100GbE MAC and PHY IP Core
Signal Name
Direction
Description
Transmit Side Signals
tx_mii_d[<w>*64-1:0]
Input
MAC to PHY connection
interface
tx_mii_c[<w>*8 -1:0]
Input
tx_mii_valid
Input
tx_mii_ready
Output
Receive Side Signals
rx_mii_d[<w>*64-1:0]
Output
PHY to MAC connection
interface
rx_mii_c[<w>*8 -1:0]
Output
rx_blocks_valid
Output
Related Information
•
Overview of IP core reset access. Includes list of reset signals and recommended reset sequence.
•
Transceiver PHY Serial Data Interface
on page 3-45
UG-01088
2014.12.15
Signals of 40-100GbE PHY‑Only IP Core Variations
3-75
Functional Description
Altera Corporation