Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 166)

Address Name Bits Description HW Reset Value Access
0x421
2WS_RDATA
[31] When asserted, the link is busy. 1b’0 R
[30] When asserted, indicates that the
slave failed to acknowledge during
the previous operation.
1b’0 R
[7:0] Result of previous read. 0x00 R
0x422
2WS_ADDR
[15:8] Slave address. 0xA0 RW
[7:0] Memory address. 0x00 RW
0x423
2WS_CMD
[1] When asserted, indicates a write
command.
0x0 RW
[0] When asserted, indicates a read. 0x0 RW
Related Information
40-100GbE IP Core Example Design on page 5-1
Altera provides an example design with the 40-100GbE IP core. This example design is ready for
compilation and can be configured on a target device. The listed registers are part of the example design.
Ethernet Glossary
Table 3-53: Ethernet Glossary
Provides definitions for some terms associated with the Ethernet protocol.
Term Definition
BIP Bit Interleaved Parity. A diagonal parity field which is carried in the periodic
alignment markers on each virtual lane, allowing isolation of a bit error to a
physical channel.
CAUI 100 gigabit attachment unit interface. (C is the symbol in Roman Numerals for
100). This is an electrical interface that which is based on a 10-lane interface with
a bandwidth of 10 Gbps per lane. (In this implementation, the PMA multiplexes
the 20 PCS lanes into 10 physical lanes.
CGMII 100 gigabit media independent interface. (C is the symbol in Roman Numerals
for 100). This is the byte-oriented interface protocol that connects the PCS and
MAC.
DIC Deficit Idle Counter. A rule for inserting and deleting idles as necessary to
maintain the average IPG. The alternative is to always insert idles which could
lead to reduced bandwidth.
UG-01088
2014.12.15
Ethernet Glossary 3-119
Functional Description Altera Corporation
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