Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 197
November
2011
Early
Access
• Corrected the following issues in the MegaCore function:
• Corrected sequence ordered set encoding in PCS.
• Corrected error control block encoding in PCS.
• Corrected pause logic to accomodate multiple pause requests.
• Timing performance improvements:
• Optimized RTL for better timing performance.
• Clocking revisions:
• clk_status and clk_csr now support 100 MHz operation in Stratix V
devices for PHY IP calibration.
• Added Stratix V resource utilization information.
• Updated definition
l
<n>
_rx_ready
to include fact that the RX MAC
can only be backpressured for a limited number of cycles; consequently,
the application should be able to accept a continuous data stream.
September
2011
Early
Access
• Feature additions:
• Added optional adapters that guarantee the start of packet is always
in lane 0.
• Added full statistics counters module.
• Modified and improved register map.
• Provided separate product ID and ordering code for 40GbE and 100GbE
MAC and PHY.
• Corrected the following issues in the MegaCore function:
• Data is no longer reversed in the adapters.
• The multicast address is used for the multicast pause frames.
• The pause state machine loads new pause times as required.
• Short frames on the TX datapath are converted correctly from 8
words to 5 words.
• Updated resource utilization numbers.
• User guide enhancements:
• Rewrote and added new sections and drawings.
• Added default values of registers after reset.
• Combined 40GbE and 100GbE in one user guide.
• Corrected description of
PMD_CMD_CONFIG
bit. Writing a 1 enables
the PMD.
• Corrected description of
PMD_CMD_CONFIG
bit. Writing a 1 enables
the PMD.
• Corrected description of
RX_AGGREGATE
register. Definitions for
bit[0] and bit[1] were reversed.
• Corrected description of
pause_quanta
.
• Corrected descriptions of Figure 3–10 on page 3–11 through Figure
3–12 on page 3–12.
• Removed
din_in_packet
from Figure 3–2 on page 3–3.
July 2010
Early
Access
Initial early access release.
D-8
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
UG-01088
2014.12.15
Altera Corporation
Additional Information