Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 58)

Figure 3-7: Reduced Bandwidth With Left-Aligned SOP Requirement
Illustrates the reduction of bandwidth that would be caused by left-aligning the SOP for the 100GbE IP
core.
Two unusable words
Example A
Example B
Four unusable words
Example A shows the minimum-sized packet of eight words. Example B shows an 11-word packet which
is the worst-case for bandwidth utilization. Assuming another packet is waiting for transmission, the
effective ingress bandwidth is reduced by 20% and 26%, respectively. Running the MAC portion of the
logic slightly faster than is required can mitigate this loss of bandwidth. Additional increases in the MAC
frequency can provide further mitigation, although doing so makes timing closure more difficult. The
wider data bus for the Avalon-ST interface also helps to compensate for the Avalon-ST left-aligned SOP
requirement.
User Interface to Ethernet Transmission
The IP core reverses the bit stream for transmission per Ethernet requirements. The transmitter handles
the insertion of the inter-packet gap, frame delimiters, and padding with zeros as necessary. The
transmitter also handles FCS computation and insertion.
The Ethernet MAC and PHY transmit complete packets. After transmission begins, it must complete with
no IDLE insertions. Between the end of one packet and the beginning of the next packet, the data input is
not considered and the transmitter sends IDLE characters. An unbounded number of IDLE characters
can be sent between packets.
Related Information
• 40GbE IP Core Without Adapters on page 3-12
Illustrates the mapping from data on the 40GbE IP core TX client interface without adapters to the
Ethernet packet fields.
• 100GbE IP Core Without Adapters on page 3-14
Illustrates the mapping from data on the 100GbE IP core TX client interface without adapters to the
Ethernet packet fields.
UG-01088
2014.12.15
User Interface to Ethernet Transmission 3-11
Functional Description Altera Corporation
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