Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 149)

Related Information
• 40-100GbE IP Core RX Filtering on page 3-21
Describes how the IP core interprets the packet length limits in
RX_FILTER_CTRL[17:8]
(for 100GbE
IP cores) and
RX_FILTER_CTRL[15:8]
(for 40GbE IP cores).
• Pause Control Frame and Non-Pause Control Frame Filtering and Forwarding on page 3-36
For more information about the IP core behavior based on the
RX_FILTER_CTRL
register bits [0], [4],
and [5].
• 40-100GbE IP Core Modes of Operation on page 3-37
Overview of filtering status.
Pause Registers
The pause registers implement the pause functionality defined in the IEEE 802.3ba-2010 100G Ethernet
Standard. You can program the pause registers to control the insertion and decoding of pause frames, to
help reduce traffic in congested networks.
Alternatively, you can use the IP core pause signals.
Table 3-42: Pause Registers
Addr Name Bit Description HW Reset
Value
Access
0x110
RECEIVE_
PAUSE_
STATUS
[16] When set to 1, indicates that a pause is in
progress.
1’b0 RO
[15:0] The time value for the pause. Reading this
field locks the pause source address.
0x140(40GbE
)0x01A0
(100GbE)
RO
0x111
RECEIVE_
SOURCE_
ADDR_LSB
[31:0] Received pause source address lsb. 0x00000000 RO
0x112
RECEIVE_
SOURCE_
ADDR_MSB
[31:0] Received pause source address msb. 0x00000000 RO
3-102 Pause Registers
UG-01088
2014.12.15
Altera Corporation Functional Description
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