Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 153)

Address Name Bit Description HW
Reset
Value
Access
0x125
Preamble
Pass-Through
Configuration
[1] Enable TX preamble pass-through. This bit has the
following valid values:
• 1’b0: Disable TX preamble pass-through.
• 1’b1: Enable TX preamble pass-through.
1’b0 RW
[0] Enable RX preamble pass-through. This bit has the
following valid values:
• 1’b0: Disable RX preamble pass-through.
• 1’b1: Enable RX preamble pass-through.
1’b0 RW
0x126 IPG_DEL_
PERIOD
[11:0] If
IPG_DEL_ENABLE[0]
has the value of one, the
IPG_DEL_PERIOD
register controls the frequency of
Idle byte deletion from the default inter-packet gap
Idle sequence.
If
IPG_DEL_ENABLE[0]
has the value of one, and
IPG_DEL_PERIOD[11:0]
has the value of N, the
MAC deletes extra Idle bytes from the inter-packet
gap in the ratio of one Idle byte for every N 8-byte
blocks.
At the default value of 2048, this deletion
compensates for Alignment Marker insertion by
the PHY (approximately 61 ppm). You can modify
the value of this register field to increase
bandwidth or adjust for clock compensation, as
needed.
12’d20
48
RW
0x127 IPG_DEL_
ENABLE
[0] Enables the inter-packet gap adjustment feature. If
this bit has the value of 1, the MAC deletes inter-
packet gap Idle bytes at the frequency specified in
the
IPG_DEL_PERIOD
register.
If this bit has the value of 0, the MAC does not
implement the inter-packet gap adjustment
feature, but instead, generates the usual
inter-packet gap, to an average IPG of 12 bytes.
1’b1 RW
Related Information
• RX Automatic Pad Removal Control on page 3-22
Describes the effect of
PAD_CONFIG[0]
on IP core behavior.
• Preamble, Start, and SFD Insertion on page 3-4
Information about the TX preamble pass-through feature and the requirements for the preamble the
client application provides to the IP core.
3-106 MAC Feature Configuration Registers
UG-01088
2014.12.15
Altera Corporation Functional Description
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