Compiling the full design and programming the fpga, Initializing the ip core, Initializing the ip core -24 – Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
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# ** Sending Packet 5...
# ** Sending Packet 6...
# ** Sending Packet 7...
# ** Sending Packet 8...
# ** Sending Packet 9...
# ** Sending Packet 10...
# ** Received Packet 1...
# ** Received Packet 2...
# ** Received Packet 3...
# ** Received Packet 4...
# ** Received Packet 5...
# ** Received Packet 6...
# ** Received Packet 7...
# ** Received Packet 8...
# ** Received Packet 9...
# ** Received Packet 10...
# **
# ** Testbench complete.
# **
# *****************************************
# ** Note: $finish : ./alt_100gbe_tb.v(197)
# Time: 32367200 ps Iteration: 0 Instance: /alt_100gbe_tb
Compiling the Full Design and Programming the FPGA
You can use the Start Compilation command on the Processing menu in the Quartus II software to
compile your design. After successfully compiling your design, program the targeted Altera device with
the Programmer and verify the design in hardware.
Related Information
•
Information about compiling your design. Chapter in volume 1 of the Quartus II Handbook.
•
Information about programming the device. Chapter in volume 3 of the Quartus II Handbook.
Initializing the IP Core
The testbench initializes the IP core. However, when you simulate or run your own design in hardware,
you must implement the initialization steps yourself.
To initialize the 40-100GbE IP core in your own design, follow these steps:
1. Drive the clock ports.
2. Reset the IP core.
3. Clear the statistics counters by writing the value of 1 to bit 3 of the general control
MAC_CMD_config
register.
Related Information
•
on page 3-51
In step 1, drive the clock ports as specified here.
•
In step 2, reset the IP core according to these recommendations.
2-24
Compiling the Full Design and Programming the FPGA
UG-01088
2014.12.15
Altera Corporation
Getting Started