Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 172
The interface between the MAC and PHY modules of the IP core is XLGMII for the 40GbE IP core and
CGMII for the 100GbE IP core. The interface between the PHY and external physical medium dependent
(PMD) optical module or other device is XLAUI for the 40GbE IP core and CAUI for the 100GbE IP core,
providing a bandwidth of either 4 or 10 × 10.3125 Gbps.
An Avalon-MM control and status (management) interface provides access to the MAC and PHY
registers in the IP core and also controls the MDIO, 2-wire serial, and PMD controllers on the PCB (for
non-40GBASE-KR4 variations) or the reconfiguration bundle (for 40GBASE-KR4 variations).
The example design is provided as a Quartus II project. The example design is crafted for you to configure
on a C2 device in a specific Altera development kit. To use a different device or development kit, you must
modify the project.
By default, the example design configures on one of the following Altera development kits, as appropriate
for the IP core target device and variation:
• 100G Development Kit, Stratix IV GT Edition
• 100G Development Kit, Stratix V GX Edition
• Transceiver Signal Integrity Development Kit, Stratix V GT Edition
• Transceiver Signal Integrity Development Kit, Stratix V GX Edition (for 40GBASE-KR4 IP cores)
To set up and configure the example design on the device, follow these steps:
1. Follow the steps in Chapter 2, Getting Started to generate your IP core. Refer to the figures for
information about the variations for which an example design can be generated.
Note: When prompted at the start of generation, you must turn on Generate example design.
2. In the Quartus II software, on the File menu, click Open Project.
3. Navigate to the example design project folder, select the Quartus Project File (.qpf), <instance_name
>_example/alt_e40_e100/example/< example_design_name >.qpf, and click Open.
4. On the Processing menu, click Start Compilation.
5. Program the targeted Altera device with the Quartus II Programmer.
Related Information
•
40-100GbE Example Design Registers
•
on page 3-116
•
•
2-Wire Serial Interface Registers
on page 3-118
•
40-100GbE IP Core File Set
Illustrates the path to the example design Quartus II project file.
•
For more information about the Avalon-MM and Avalon-ST protocols, including timing diagrams.
•
For information about the Altera development kits that the example designs target.
•
For information about programming an Altera device, refer to the "Device Programming" section.
A-4
40-100GbE IP Core Example Design
UG-01088
2014.12.15
Altera Corporation
40-100GbE IP Core Example Design