Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 79)

Error Conditions on the RX Datapath
The RX MAC indicates error conditions by asserting
l<n>_rx_error
. The following error conditions are
defined:
• Received frame terminated early or with an error
• Received frame has a CRC error
• Error characters received from PHY
• Receive frame is too short (less than 64 bytes) or too long (longer than the maximum specified length)
40GbE Lower Rate 24.24 Gbps MAC and PHY
The 40GbE MAC and PHY IP core configured on certain device speed grades can run at 24.24 Gbps with
a 4 x 6.25 Gbps external interface. To generate a 40GbE IP core that runs at the 24.24 Gbps rate, the
Quartus II software generates the PHY with a data rate of 6250.0 Mbps, instead of the 10312.5 Mbps data
rate for the normal 40GbE IP core variations.
Related Information
40-100GbE IP Core Device Speed Grade Support on page 1-5
Information about the device speed grades that support the 24.24 Gbps IP core variation.
100GbE CAUI–4 PHY
The 100GbE PHY IP core configured in a Stratix V GT device supports CAUI-4 PCS and PMA at 4 x
25.78125 Gbps. The PHY and CAUI PHY interfaces are interoperable with the 100GbE MAC.
The 100GbE CAUI–4 PHY is only available in duplex mode. The 100GbE CAUI–4 PHY, and all other
Stratix V variants, require an external reconfiguration controller.
Related Information
• 40-100GbE IP Core Device Speed Grade Support on page 1-5
Information about the device speed grades that support the 100GbE CAUI–4 Gbps IP core variation.
• External Reconfiguration Controller on page 3-32
External Reconfiguration Controller
40GbE and 100GbE IP cores that target a Stratix IV, Stratix V, or Arria V GZ device, and that include a
PHY, require an external reconfiguration controller.
Altera recommends that you configure an Altera ALTGX_RECONFIG megafunction for your Stratix IV
40-100GbE IP core, and an Altera Transceiver Reconfiguration Controller for your Arria V GZ or Stratix
V 40-100GbE IP core.
Related Information
• External Transceiver Reconfiguration Controller on page 2-11
Information about configuring and connecting the Altera Transceiver Reconfiguration Controller.
Includes signal descriptions.
• 40-100GbE IP Core Example Design on page 5-1
Refer to the Stratix V example designs for a guide to connecting Altera Transceiver Reconfiguration
Controllers to your 40-100GbE IP core.
3-32 Error Conditions on the RX Datapath
UG-01088
2014.12.15
Altera Corporation Functional Description
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