Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 43)

Generating the 40-100GbE Testbench
A single procedure generates both the testbench and the example project. To generate the testbench and
example project:
1. Follow the steps in
Specifying the 40-100GbE IP Core Parameters and Options to parameterize your
IP core.
2. Generate the IP core by clicking Generate.
Note: When prompted at the start of generation, you must turn on Generate example design.
Turning on Generate example design is the only process that generates a functional testbench
and a functional example design.
When the IP core is generated in <working directory>, the testbench and example project are generated
in <working directory>
/
<IP core variation>
/_example/alt_e40_e100
.
The directory with the testbench and example project has two subdirectories:
•
example
, which contains the example design project
• example_testbench , which contains the demonstration testbench
Simulating with the Modelsim Simulator
To run the simulation in the ModelSim simulation tool, follow these steps:
1. Change directory to the <variation_name>
_example/alt_e40_e100/example_testbench directory.
2. In the command line, type:
vsim -c -do run_vsim.do
The example testbench will run and pass.
Simulating with the NCSim Simulator
To run the simulation in the NCSim simulation tool, follow these steps:
1. Change directory to the <variation_name>
_example/alt_e40_e100/example_testbench directory.
2. In the command line, type:
sh run_ncsim.sh
The example testbench will run and pass.
Simulating with the VCS Simulator
To run the simulation in the VCS simulation tool, follow these steps:
1. Change directory to the <variation_name>
_example/alt_e40_e100/example_testbench directory.
2. In the command line, type:
sh run_vcs.sh
The example testbench will run and pass.
Testbench Output Example: 40GbE IP Core with Adapters
This section shows successful simulation using the 40GbE IP core with adapters testbench ( alt_40gbe_
tb.sv ). The testbench connects the Ethernet TX lanes to the Ethernet RX lanes, so that the IP core is in an
external loopback configuration. In simulation, the testbench resets the IP core and waits for lane
alignment and deskew to complete successfully. The packet generator sends ten packets on the Ethernet
TX lanes and the packet checker checks the packets when the IP core receives them on the Ethernet RX
lanes.
UG-01088
2014.12.15
Generating the 40-100GbE Testbench 2-21
Getting Started Altera Corporation
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