Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 72)

• Pause Registers on page 3-102
40-100GbE IP Core RX Data Bus Interfaces
This section describes the RX data bus at the user interface and includes the following topics:
40-100GbE IP Core User Interface Data Bus on page 3-6
40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) on page 3-25
40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) on page 3-28
100GbE IP Core RX Client Interface Examples on page 3-30
Error Conditions on the RX Datapath on page 3-32
40-100GbE IP Core User Interface Data Bus
Table 3-4: User Interface Width Depends on IP Core Variation
The 40-100GbE IP core provides two different client interfaces: the Avalon-ST interface and a custom interface.
The Avalon-ST interface requires adapters and the custom streaming interface does not require adapters.
Client Interface
Data Bus Width (Bits)
40GbE IP Core 100GbE IP Core
Custom streaming interface (no
adapters)
128 320
Avalon-ST interface (with
adapters)
256 512
40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface)
The adapter for the RX interface of the 100GbE IP core increases the bus width from 5 words (320 bits) to
8 words (512 bits). The adapter for the RX interface of the 40GbE IP core increases the bus width from 2
word (128 bits) to 4 words (256 bits). The Avalon-ST interface always locates the SOP at the MSB,
simplifying the interpretation of incoming data.
The RX MAC acts as a source and the client acts as a sink in the receive direction.
UG-01088
2014.12.15
40-100GbE IP Core RX Data Bus Interfaces 3-25
Functional Description Altera Corporation
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