Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 33)

In the top-level wrapper file for your simulation project, you can set the
FAST_SIMULATION
parameter to
enable simulation optimization. Parameters are set through the IP core parameter editor. In general, you
should not change them manually. The only exception is the
FAST_SIMULATION
parameter. You should set
the
FAST_SIMULATION
parameter on the PHY blocks by adding the following line to the top-level wrapper
file:
defparam <dut instance>.FAST_SIMULATION = 1;
Note: You can use the example testbench as a guide for setting the simulation parameters in your own
simulation environment. This line is already present in the Altera-provided testbench that is
generated with the IP core.
Related Information
• Simulating the 40-100GbE IP Core With the Testbenches on page 2-20
Instructions to simulate the 40GbE or 100GbE IP core with the IP core appropriate testbench you can
generate.
• 40-100GbE IP Core Testbenches on page 2-14
Altera provides a testbench and example design with most variations of the 40-100GbE IP core. The
testbench is available for simulation of your IP core, and the example design can be run on hardware.
This topic describes the testbench provided with the 40-100GbE IP core. For a complete list of models
or libraries required to simulate your IP core, refer to the scripts provided with the testbench.
• Simulating Altera Designs
Chapter in volume 3 of the Quartus II Handbook that provides information about simulating Altera IP
cores.
Integrating Your IP Core in Your Design
When you integrate your IP core instance in your design, you must pay attention to the following items:
Pin Assignments on page 2-11
External Transceiver Reconfiguration Controller on page 2-11
Placement Settings for the 40-100GbE IP Core on page 2-14
Pin Assignments
When you integrate your 40-100GbE IP core instance in your design, you must make appropriate pin
assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals
while you are simulating and not ready to map the design to hardware.
Related Information
Quartus II Help
For information about the Quartus II software, including virtual pins and the IP Catalog.
External Transceiver Reconfiguration Controller
40-100GbE IP cores that include the PHY component require an external reconfiguration controller to
compile and to function correctly in hardware.
UG-01088
2014.12.15
Integrating Your IP Core in Your Design 2-11
Getting Started Altera Corporation
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