Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 31)

Parameter Type Range Default
Setting
Parameter Description
Include FEC
sublayer
Boolean • True
• False
False If this parameter is turned on, the IP core includes
logic to implement FEC.
Set FEC_ability
bit on power
up/reset
Boolean • True
• False
True
If this parameter is turned on, the IP core sets the
FEC ability bit (40GBASE-KR4 register offset 0xB0,
bit 16) on power up and reset.
Set FEC_Enable
bit on power
up/reset
Boolean • True
• False
True
If this parameter is turned on, the IP core sets the
FEC enable bit (40GBASE-KR4 register offset 0xB0,
bit 18) on power up and reset. If you turn on this
parameter but do not turn on Set FEC_ability bit on
power up/reset, this parameter has no effect: the IP
core cannot specify the value of 1 for FEC Requested
without specifying the value of 1 for FEC Ability.
Set FEC_Error_
indication_
ability bit on
power up/reset
Boolean • True
• False
True
If this parameter is turned on, the IP core is
programmed by default (40GBASE-KR4 register
offset 0xB0, bit 17) to report decoding errors to the
PCS.
Use M20K for
FEC Buffer (if
available)
Boolean • True
• False
True
If this parameter is turned on, the IP core is
configured with a pipelined FEC buffer to support the
Quartus II software in inferring M20K memory.
Turning on this parameter potentially saves device
resources.
Table 2-3: 40-100GbE PHY Parameter Settings
Lists the PHY parameters that are configured automatically based on parameter values you select in the 40G/100G
Ethernet parameter editor.
Parameter 40GbE Value
40GBASE-KR4 Value
100GbE Value 40GbE at 24.24 Gbps 100GbE at CAUI–4
Lanes
4 10 4 4
Data rate per lane 10312.5 Mbps
10312.5 Mbps 6250.0 Mbps 25781.25 Mbps
Available PHY
reference clock
frequencies
644.53125 MHz
322.265625 MHz 644.53125 MHz
322.265625 MHz 390.625 MHz
195.3125 MHz 644.53125 MHz
Related Information
• Clocks on page 3-51
The range and default settings for the PHY reference frequency parameter depend on the PHY
configuration parameter value. The PHY reference frequency value is the required frequency of the
transceiver reference clock or transceiver reference clocks.
UG-01088
2014.12.15
IP Core Parameters 2-9
Getting Started Altera Corporation
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