Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 93)

40GBASE-KR4 IP Core Variations
The 40GBASE-KR4 IP core supports low-level control of analog transceiver properties for link training
and auto-negotiation in the absence of a predetermined environment for the IP core. For example, an
Ethernet IP core in a backplane may have to communicate with different link partners at different times.
When it powers up, the environment parameters may be different than when it ran previously. The
environment can also change dynamically, necessitating reset and renegotiation of the Ethernet link.
The 40-100GbE IP core 40GBASE-KR4 variations implement the IEEE Backplane Ethernet Standard
802.3ap-2007. The 40-100GbE IP core provides this reconfiguration functionality in Stratix V devices by
configuring each physical Ethernet lane with an Altera Backplane Ethernet 10GBASE-KR PHY IP core if
you turn on Enable KR4 in the 40-100GbE parameter editor. The parameter is available in variations
parameterized with these values:
• Device family: Stratix V
• MAC configuration: 40GbE
• Core option: "PHY" or "MAC & PHY"
• PHY configuration: 40Gbps (4 x 10)
• Duplex mode: Full Duplex
The PHY IP core includes the option to implement the following features:
• KR auto-negotiation provides a process to explore coordination with a link partner on a variety of
different common features. The 40GBASE-KR4 variations of the 40-100GbE IP core can auto-
negotiate only to a 40GBASE-KR4 configuration. Turn on the Enable KR4 Reconfiguration and
Enable Auto-Negotiation parameters to configure support for auto-negotiation.
• Link training provides a process for the IP core to train the link to the data frequency of incoming
data, while compensating for variations in process, voltage, and temperature. Turn on the Enable KR4
Reconfiguration and Enable Link Training parameters to configure support for TX link training.
To enable RX link training, you must also turn on the Enable RX equalization parameter. Two
options are available for TX link training:
• A built-in TX adaptation algorithm.
• A microprocessor interface to support manual control of the link training process. Turn on the
Enable microprocessor interface parameter to configure this support.
• After the link is up and running, forward error correction (FEC) provides an error detection and
correction mechanism to enable noisy channels to achieve the Ethernet-mandated bit error rate (BER)
of 10 -12 . Turn on the Include FEC sublayer to configure support for FEC.
The 40GBASE-KR4 IP core variations include separate link training and FEC modules for each of the four
Ethernet lanes, and a single auto-negotiation module. You specify the master lane for performing auto-
negotiation in the parameter editor, and the IP core also provides register support to modify the selection
dynamically.
The 40GBASE-KR4 IP core is designed to connect to a reconfiguration bundle, which includes the Altera
Transceiver Reconfiguration Controller and logic to assist in reconfiguring the transceivers into the
different modes of operation (AN, LT, and FEC data mode or non-FEC data mode). Altera provides the
testbench and example design to assist you in integrating your 40GBASE-KR4 IP core into your complete
design. The testbench and design example include the reconfiguration bundle. You can examine the
reconfiguration bundle for an example of how to drive and connect the 40GBASE-KR4 IP core.
The 40GBASE-KR4 IP core variations provide two interfaces to control these processes.
3-46 40GBASE-KR4 IP Core Variations
UG-01088
2014.12.15
Altera Corporation Functional Description
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