Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 42)

Simulating the 40‑100GbE IP Core With the Testbenches
You can simulate the 40-100GbE IP core using the Altera-supported versions of the Mentor Graphics
ModelSim ® SE, Cadence NCSim, and Synopsys VCS simulators for the current version of the Quartus II
software.
The example testbenches simulate packet traffic at the digital level. The testbenches do not require special
SystemVerilog class libraries.
The top-level testbench file for non-40GBASE-KR4 variations consists of a simple packet generator and
checker and one core in a loopback configuration. The packet generator skews and reorders its
transmitter digital output to emulate actual transceiver behavior and optical cabling lane permutations.
The top-level testbench file for 40GBASE-KR4 variations consists of a symmetric arrangement with two
IP cores and traffic between them. For each IP core there is a packet generator to send traffic on the TX
side of the IP core and a packet checker to check the packets it receives from the other IP core. The two IP
cores communicate with each other through their Ethernet link, in which the testbench injects random
skew. The 40GBASE-KR4 testbench connects each IP core to a reconfiguration bundle, and exercises
auto-negotiation, link training, and data mode.
The example testbenches contain the test files and run scripts for the ModelSim, Cadence, and Synopsys
simulators. The run scripts use the file lists in the wrapper files. When you launch a simulation from the
original directory, the relative filenames in the wrapper files allow the run script to locate the files
correctly. You can access design files from any location if your directory structure matches the structure
assumed in the run script path names.
The following examples provide directions for generating the testbench and running tests with the
ModelSim, Cadence, and Synopsys simulators.
Generating the 40-100GbE Testbench on page 2-21
Simulating with the Modelsim Simulator on page 2-21
Simulating with the NCSim Simulator on page 2-21
Simulating with the VCS Simulator on page 2-21
Testbench Output Example: 40GbE IP Core with Adapters on page 2-21
Testbench Output Example: 100GbE IP Core with Adapters on page 2-23
Related Information
• Simulating the IP Core on page 2-10
• 40-100GbE IP Core Testbenches on page 2-14
Altera provides a testbench and an example design with most variations of the 40-100GbE IP core. The
testbench is available for simulation of your IP core, and the example design targets a C2 speed grade
device and can be run on hardware. You can run the testbench to observe the IP core behavior on the
various interfaces in simulation.
2-20 Simulating the 40‑100GbE IP Core With the Testbenches
UG-01088
2014.12.15
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