Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 127)

Lock Status Registers on page 3-84
Bit Error Flag Registers on page 3-86
PCS Hardware Error Register on page 3-87
BER Monitor Register on page 3-87
Test Mode Register on page 3-88
Test Pattern Counter Register on page 3-88
Link Fault Signaling Registers on page 3-88
MAC and PHY Reset Registers on page 3-89
PCS-VLANE Registers on page 3-91
PRBS Registers on page 3-92
40GBASE-KR4 Registers on page 3-92
MAC Configuration and Filter Registers on page 3-99
Pause Registers on page 3-102
MAC Hardware Error Register on page 3-104
CRC Configuration Register on page 3-105
MAC Feature Configuration Registers on page 3-105
MAC Address Registers on page 3-107
Statistics Registers on page 3-108
Related Information
Control and Status Interface on page 3-51
Transceiver PHY Control and Status Registers
The TX serial rate (PCS clock) is based on the input transceiver reference clock and should be precise and
stable. The RX serial rate is recovered from the remote system. The RX serial clock typically shows some
instability during lock acquisition.
In variations that target a Stratix IV device, the registers in the transceiver PHY provide dynamic access to
the analog configuration capability on a per channel (pin) basis. You can also use these registers to place
the transceivers in loopback mode for diagnostic or error injection testing. In loopback mode, the TX
output connects to the corresponding RX channel.
3-80 Transceiver PHY Control and Status Registers
UG-01088
2014.12.15
Altera Corporation Functional Description
Send Feedback