Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 45

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Testbench Output Example: 100GbE IP Core with Adapters

This section shows successful simulation using the 100GbE IP core with adapters testbench (

alt_100gbe_

tb.sv

). The testbench connects the Ethernet TX lanes to the Ethernet RX lanes, so that the IP core is in an

external loopback configuration. In simulation, the testbench resets the IP core and waits for lane

alignment and deskew to complete successfully. The packet generator sends ten packets on the Ethernet

TX lanes and the packet checker checks the packets when the IP core receives them on the Ethernet RX

lanes.
The successful testbench run displays the following output:

# *****************************************
# ** 100g Ethernet Testbench
# **
# **
# ** Target Device: Stratix IV
# ** IP Configuration: 100 Gbe
# ** Variant Name: abc
# ** Status Clock Rate: 50000 KHz
# ** Statistics Registers: Enabled
# **
# ** This variant is MAC & PHY
# ** Interface: Avalon-ST
# *****************************************
# ** Reseting the IP Core...
# **
# **
# *****************************************
# ** Waiting for alignment and deskew...
# **
# **
# ** Virutal lane locked: None (lanes left: 20) |@@@@@@@@@@@@@@@@@@@@|
# ** Virtual lane locked: 0 (lanes left: 19) |@@@@@@@@@@@@@@@@@@@\|
# ** Virtual lane locked: 3 (lanes left: 18) |@@@@@@@@@@@@@@@@/@@\|
# ** Virtual lane locked: 5 (lanes left: 17) |@@@@@@@@@@@@@@/@/@@\|
# ** Virtual lane locked: 11 (lanes left: 16) |@@@@@@@@/@@@@@/@/@@\|
# ** Virtual lane locked: 7 (lanes left: 15) |@@@@@@@@/@@@/@/@/@@\|
# ** Virtual lane locked: 12 (lanes left: 14) |@@@@@@@\/@@@/@/@/@@\|
# ** Virtual lane locked: 14 (lanes left: 13) |@@@@@\@\/@@@/@/@/@@\|
# ** Virtual lane locked: 4 (lanes left: 12) |@@@@@\@\/@@@/@/\/@@\|
# ** Virtual lane locked: 8 (lanes left: 11) |@@@@@\@\/@@\/@/\/@@\|
# ** Virtual lane locked: 2 (lanes left: 10) |@@@@@\@\/@@\/@/\/\@\|
# ** Virtual lane locked: 18 (lanes left: 9) |@\@@@\@\/@@\/@/\/\@\|
# ** Virtual lane locked: 1 (lanes left: 8) |@\@@@\@\/@@\/@/\/\/\|
# ** Virtual lane locked: 16 (lanes left: 7) |@\@\@\@\/@@\/@/\/\/\|
# ** Virtual lane locked: 17 (lanes left: 6) |@\/\@\@\/@@\/@/\/\/\|
# ** Virtual lane locked: 19 (lanes left: 5) |/\/\@\@\/@@\/@/\/\/\|
# ** Virtual lane locked: 15 (lanes left: 4) |/\/\/\@\/@@\/@/\/\/\|
# ** Virtual lane locked: 13 (lanes left: 3) |/\/\/\/\/@@\/@/\/\/\|
# ** Virtual lane locked: 9 (lanes left: 2) |/\/\/\/\/@/\/@/\/\/\|
# ** Virtual lane locked: 10 (lanes left: 1) |/\/\/\/\/\/\/@/\/\/\|
# All lanes locked. Starting deskew at time 29531200
# ** Virtual lane locked: 6 (lanes left: 0) |/\/\/\/\/\/\/\/\/\/\|
# Deskew complete at time 31243200
# ** All virtual lanes locked and deskewed, ready for data
|--------------------|
# *****************************************
# ** Starting TX traffic...
# **
# **
# ** Sending Packet 1...
# ** Sending Packet 2...
# ** Sending Packet 3...
# ** Sending Packet 4...

UG-01088

2014.12.15

Testbench Output Example: 100GbE IP Core with Adapters

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