10gbase-kr registers, 10gbase-kr phy register definitions, For details – Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 174: Lane 1. (refer to, 10gbase-kr, Phy register definitions, 10gbase-kr phy register, Definitions, Register 0xd3 for lane 1 link training. (refer to, Register 0xd4 for lane 1 link training. (refer to

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10gbase-kr registers, 10gbase-kr phy register definitions, For details | Lane 1. (refer to, 10gbase-kr, Phy register definitions, 10gbase-kr phy register, Definitions, Register 0xd3 for lane 1 link training. (refer to, Register 0xd4 for lane 1 link training. (refer to | Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual | Page 174 / 199 10gbase-kr registers, 10gbase-kr phy register definitions, For details | Lane 1. (refer to, 10gbase-kr, Phy register definitions, 10gbase-kr phy register, Definitions, Register 0xd3 for lane 1 link training. (refer to, Register 0xd4 for lane 1 link training. (refer to | Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual | Page 174 / 199
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