Freescale Semiconductor MCF5480 - Manual (Page 1025)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor Index-11
USB
application interface update (IFUR) 29-22
application interrupt mask (USBAIMR) 29-17
application interrupt status (USBIASR) 29-16
bitstuffing error counter (BSECNT) 29-24
bmrequest type (BMRTR) 29-31
brequest type (BRTR) 29-32
configuration attribute (CFGAR) 29-19
configuration interface (IFRn) 29-22
configuration value (CFGR) 29-19
control (USBCR) 29-10
counter overflow (CNTOVR) 29-26
CRC error counter (CRCECNT) 29-24
descriptor RAM control (DRAMCR) 29-12
descriptor RAM data (DRAMDR) 29-13
device speed (SPEEDR) 29-20
dropped packet counter (DPCNT) 29-24
endoint n sync frame 29-33
endpoint info (EPINFO) 29-18
endpoint n attribute control 29-27
endpoint n FIFO alarm (EPnFAR) 29-44
endpoint n FIFO control (EPnFCR) 29-42
endpoint n FIFO data (EPnFDR) 29-39
endpoint n FIFO RAM configuration
(EPnFRCFGR) 29-38
endpoint n FIFO read pointer (EPnFRP) 29-45
endpoint n FIFO status (EPnFSR) 29-40
endpoint n FIFO write pointer (EPnFWP) 29-45
endpoint n interface number 29-29
endpoint n interrupt mask (EPnIMR) 29-37
endpoint n interrupt status (EPnISR) 29-35
endpoint n last read frame pointer (EPnLRFP) 29-46
endpoint n last write frame pointer (EPnLWFP) 29-47
endpoint n max packet size 29-28
endpoint n status 29-30
endpoint n status and control (EPnSTAT) 29-34
endpoint transaction number (EPTNR) 29-21
error counter (PIDECNT) 29-25
frame number (FRMNUMR) 29-21
framing error counter (FRMECNT) 29-25
interrupt mask (USBIMR) 29-15
interrupt status (USBISR) 29-14
packet passed count (PPCNT) 29-23
status (USBSR) 29-9
transmitted packet counter (TXPCNT) 29-26
windex (WINDEXR) 29-33
wlength (WLENGTHR) 29-33
wvalue (WVALUER) 29-32
S
Sample Point 21-29
S-clock 21-28
SDRAM controller
block diagram 18-2
commands
ACTV 18-10
LMR, LEMR 18-11
PALL 18-11
PDWN 18-13
READ 18-10
REF 18-13
SREF 18-13
WRITE 18-10
configuration 18-4
connections 18-6–18-7
example 18-24–18-34
initialization 18-13, 18-34
interface configuration 18-25–18-33
page management 18-15
registers
chip select configuration (CSnCFG) 18-18
configuration 1 (SDCFG1) 18-21
configuration 2 (SDCFG2) 18-23
control (SDCR) 18-20
drive strength (SDRAMDS) 18-17
mode/extended mode (SDMR) 18-19
signals
address bus (SDADDRn) 18-2
bank address (SDBAn) 18-2
chip selects (SDCSn) 18-3
clock (SDCLKn) 18-3
clock enable (SDCKE) 18-4
column address strobe (CAS) 18-3
data bus (SDDATAn) 18-2
data strobe (SDDQSn) 18-3
data strobe (SDRDQS) 18-4
inverted clock (SDCLKn) 18-3
memory supply (SDVDD) 18-4
reference voltage (VREF) 18-4
row address strobe (RAS) 18-3
write data byte mask (SDDMn) 18-3
write enable (SDWE) 18-3
transfer size 18-15
SEC
block diagram 22-2
controller 22-10
crypto-channel 22-3, 22-11, 22-18
descriptors 22-56–22-67
buffer 22-21
chaining 22-60
classes 22-64
null fields 22-61
static 22-65
structure 22-56